The Pass Catalog
All counts, names, and symbols on this page apply to
neuronx_cc2.24.5133.0+58f8de22 (cp310 wheel; cp311/cp312 carry the same registries — only Cython hash suffixes and binary VAs drift). The four stages live in four binaries:neuronxcc/starfish/bin/hlo-opt(BuildID93dd8bd9bd4c697b, not stripped), the MLIR pipeline inside that samehlo-opt, the Cython pass modules underneuronxcc/starfish/penguin/, andneuronxcc/starfish/lib/libwalrus.so(BuildID92b4d331…). Treat every count as version-pinned — the re-derivation recipes in §5 re-run against any wheel.
Abstract
This appendix is the single consolidated index of every compiler pass in neuronx-cc, across all four optimization stages that a graph traverses on its way from XLA HLO to a packaged NEFF. There is no one place in the binaries where all four registries meet — each stage owns its own name→pass mechanism, in its own binary, with its own selection rule — so this page is the meeting point. It exists to answer one question for a reimplementer or a debugger: given a pass name, which stage owns it, what class does it construct, where in the pipeline does it run, and which wiki page documents it.
The four stages and their headline counts, each re-derived from the binary in §5:
- hlo-opt B-strand — the
--passesregistry of HLO-level rewrites, 112 registered names → 112 classes, keyed bypass->name(). The source of truth is 4.1. - hlo2penguin C-strand (MLIR) — the imperatively-built
mhlo/stablehlopass pipeline that lowers optimized HLO topenguin.pytext. 32 MHLO steps; the StableHLO fork is the same spine with 5 insertions = 37 steps. The source of truth is 4.32. - Penguin middle-end — a catalog of Cython pass modules (no flat registry), sequenced at run time by
SharedCodeGenFlowgenerators. 248 total pass modules across four directories (71 + 131 + 6 + 40), of which ~8–10 in the twotransforms/dirs are helper libraries, notPassclasses. The source of truth is 5.7. - walrus backend — the
GeneratorRegistrationname→factory registry, 150 registered names collapsing to 121 distinct C++ classes (10 classes multi-registered), scheduled into ~180 pipeline steps. The source of truth is 8.1.
Each stage uses a structurally different name→pass mechanism, and that difference is itself the most useful thing this catalog records — a reimplementer who assumes one registry for the whole compiler will get all four wrong. §0 lays the four mechanisms side by side. §1–§4 index each stage's passes by family, with the documenting page per family. The full row-level tables are not reproduced here — they live in the four normative pages — because pasting 112 + 37 + ~240 + 150 rows would be a dump, not an index; this page is the map to those tables, with the cross-stage counts reconciled in one place.
This is a reference catalog, not an algorithm walkthrough; its value is completeness and correct cross-stage ordering. Confidence is per-row in §5: the four name counts (112 / 32+5 / 248 / 150) are CONFIRMED on the binary; the 121-class walrus total is STRONG (derived); the Penguin run order is STRONG (from the version-counter source-order trace).
| Stage 1 — hlo-opt | xla::hilo::RegisterHiloHloPasses @ 0x1e72270 → llvm::StringMap; 112 names (4.1) |
| Stage 2 — MLIR | hilo::registerMHLOPasses @ 0x1ee12f0 (32) / registerStableHLOPasses @ 0x1ee2120 (37) (4.32) |
| Stage 3 — Penguin | SharedCodeGenFlow generators → PassConstructorBuilder; 248 modules (5.7) |
| Stage 4 — walrus | GeneratorRegistration::registerGenerator → _Hashtable; 150 names → 121 classes (8.1) |
| Grand pass-name total | 112 + 37 + ~240 + 150 ≈ ~539 named pass positions across the four stages |
| Selection | Stage 1: --passes/--skip-pass (XLA DebugOptions) · Stage 2: per-pass CompileConfig gate byte · Stage 3: OptLevel + required/optional · Stage 4: --pass (registry) + optlevel builder |
0. The Four Registry Shapes
The single most important cross-stage fact is that each stage binds a pass name to a pass object by a different mechanism. They are not four instances of one design; they are four designs. A reimplementer must reproduce each one separately.
| Stage | Binary | Name→pass mechanism | Key derivation | Selection / ordering |
|---|---|---|---|---|
| 1 hlo-opt | hlo-opt (C++) | llvm::StringMap<std::function<unique_ptr<HloPass>()>> filled by 112 RegisterHloPass calls | key = pass->name() read back at registration (vtable vptr+0x10) — not a literal in the registrar | XLA DebugOptions whitelist/blacklist; run-list ordered by the driver outside the registrar |
| 2 MLIR | hlo-opt (C++) | no registry — imperative pm.addPass(...) / addNestedPass<func::FuncOp>(...) spine | none; passes are constructed inline by create<Name>Pass() factories | ordering is the literal addPass source order; each gated on a CompileConfig byte |
| 3 Penguin | Cython .so per pass | no registry — yield PassType(Class, kwargs, required|optional) into a PassConstructorBuilder folded via += | none; the PassType carries the class object directly | OptLevel staged-skip at flow level + per-spec required/optional + clOptBool toggles |
| 4 walrus | libwalrus.so (C++) | _Hashtable<string, function<unique_ptr<BackendPass>(PassOptions)>> filled by 150 register_generator_*__ static initializers | key = the literal string passed to registerGenerator("<name>", …) | --pass <name> via getGenerator; optlevel pipeline builders call addPass("<name>"); granularity per call-site |
Two stages have a real string-keyed registry (1, 4); two build the pipeline imperatively with no name table at all (2, 3). The two registries even differ in where the key comes from: hlo-opt reads the key back off name() at registration (so the registrar source never shows it), while walrus passes the literal name straight into registerGenerator. That asymmetry is why recovering the 112 hlo-opt keys required walking each factory to its vtable, whereas the 150 walrus names grep straight out of the symbol table.
GOTCHA — "pass count" means four different things. Stage 1's 112 is registered names = classes (1:1). Stage 4's 150 is registered names, which is not the class count (121) — 10 classes answer to several names. Stage 3's 248 is modules, which is not the pass-class count (~8–10 are helper libs) and not the run-list length (a flow runs a subset, some passes twice). Stage 2's 32/37 is pipeline steps, every one gated, so the executed count depends on the CompileConfig. A single "total passes" number for the compiler is meaningless; always say which of name/class/module/step you mean.
1. Stage 1 — hlo-opt B-strand (112 passes)
xla::hilo::RegisterHiloHloPasses registers 112 passes into an llvm::StringMap keyed by each pass's name(). CONFIRMED — an objdump of the registrar body (0x1e72270–0x1e744af) shows exactly 112 call instructions targeting RegisterHloPass (0x1ebc3f0). Of the 112, 87 override their own Run (vtable+0x18) and 25 are OpExpander passes sharing xla::OpExpanderPass::Run @ 0x29f0bb0 and overriding InstructionMatchesPattern (vtable+0x28). Of provenance, 3 are stock XLA classes reused unchanged (tuple-simplifier, call-inliner, dce); the rest are Neuron-authored.
The 112-row name→class→vtable→entry table is not duplicated here — it is the canonical table in 4.1 §2. Below is the index of that table by family, pointing each family at the 4.x page that documents it.
| Family (registration-order span) | Representative names | Documenting page | Conf |
|---|---|---|---|
| Stock XLA (reused) | tuple-simplifier call-inliner dce | 4.1 §4 | CONFIRMED |
| Legalize / intrinsics / compare | legalize-intrinsics legalize-compare | intrinsics-compare-legalize | CONFIRMED |
| Softmax / TopK / ArgMax legalize | legalize-softmax legalize-topk legalize-aws-neuron-arg-max lower-argminmax-custom-call | softmax-legalize, topk-legalize, argmax-argmin-legalize | CONFIRMED |
| Quantize / scaled-matmul | legalize-quantize-mx legalize-scaled-matmul | mx-fp8-legalization, int8-quantize-legalization | CONFIRMED |
| Collectives → custom-call | convert-collectives-to-custom-call convert-fs-patterns-to-cc | collectives-to-customcall | CONFIRMED |
| CC-op decompose / legalize | decompose-cc-ops legalize-cpu-cc-ops legalize-ccops-for-tensorizer trivial-cc-removal | ccops-decompose-legalize | CONFIRMED |
| Collective combiners | all-gather-combiner reduce-scatter-combiner all-reduce-combiner | collective-combiners | CONFIRMED |
| Stream-ID / channel-ID | collective-stream-id-checker aws_neuron_collective_stream_id_injector neuron_unique_channel_id_enforcer | collective-stream-channel-id | CONFIRMED |
| Flip-collective OpExpanders | aws_neuron_flip_all_gather_* aws_neuron_flip_reduce_* | flip-collective-opexpander | CONFIRMED |
| AllReduce→ReduceScatter / DynSlice | aws_neuron_rewrite_all_reduce_dynamic_slice[_multiple_groups] | allreduce-dynslice-rewrites | CONFIRMED |
| CollectivePermute → AllGather | collective-permute-to-all-gather aws_neuron_rewrite_collective_permute | collectivepermute-to-allgather | CONFIRMED |
| Looped-einsum | neuron_looped_einsum_replacer neuron_looped_einsum_token_replacer | looped-einsum-collective-matmul | CONFIRMED |
| Int / scalar-reduce decompose | aws_neuron_decompose_int_all_reduce aws_neuron_decompose_scalar_reduce | int-scalar-reduce-decomposition | CONFIRMED |
| While-loop unroll / trip-count | while_loop_unroller unroll-while-loop aws_neuron_rewrite_all_gather_trip_count | whileloop-unroll-tripcount | CONFIRMED |
| While-loop collective code-motion | neuron-while-loop-all-reduce-code-motion neuron_move_*_while_loop | whileloop-collective-codemotion | CONFIRMED |
| Boundary markers / layer-cut | canonicalize-boundary-marker boundary-marker-removal | boundary-markers-layer-cut | CONFIRMED |
| Control-dep reification | preserve-control-deps | control-dep-reification | CONFIRMED |
| Layout passes | io-layout-normalization aws_neuron_ensure_descending_layout_in_root | layout-passes | CONFIRMED |
| I/O-alias family | remove-aliases add-must-aliases add-may-aliases flip-must-aliases flip-may-aliases aws_neuron_alias_to_must_alias aws_neuron_buffer_donation_to_alias | io-alias-family | CONFIRMED |
| Concat optimizations | simplify-concat slice-of-concat-optimizer neuron_repeated_dus_to_concat | concat-optimizations | CONFIRMED |
| DUS/DS simplifier / mover | neuron-dus-ds-index-simplifier dynamic-slice-mover dynamic-slice-transpose | dus-ds-simplifier | CONFIRMED |
| Dedup (param / kernel) | neuron-preprocess-kernel-duplicate-remover neuron_all_gather_duplicate_remover | dedup-passes | CONFIRMED |
| InstCombine peephole | neuron-hlo-inst-comb aws_neuron_common_instruction_elimination eliminate-redundant-compare aws_neuron_resolve_self_comparison | instcombine-peephole | CONFIRMED |
| Precision / upcast | upcast-all-to-fp32 batch-norm-training-upcast rewrite-module-dtype neuron-int-matmul-downcast | precision-upcast-passes | CONFIRMED |
| Calibration / scale | (scale/zero-point flow) | calibration-scale-flow | STRONG |
| NKI / native lowering | lower-to-nki-kernels lower-to-custom-native-kernel | hlo-to-native-kernel-lowering | CONFIRMED |
| Misc / cleanup sweep | stub metadata-naming aws_neuron_default_metadata opt-barrier-removal inline-weights replace-rng inject-prints inject-numerical-errors | hlo-misc-cleanup-sweep | CONFIRMED |
NOTE — the registration order (1..112) in 4.1 §2 is the registrar's emission order and serves as the default-pipeline proxy — it is not the run order. The executed run-list is a driver-supplied ordered name subset assembled outside
hlo-opt's registrar, then filtered by--passes(whitelist) /--skip-pass(blacklist). The family table above is sorted by topic, not by registration index; cross-reference 4.1 §2 for the exact#.
2. Stage 2 — hlo2penguin C-strand MLIR pipeline (32 + 5 = 37 steps)
After the 112 B-strand passes run, optimized HLO is imported into mhlo and a fixed, imperatively-built MLIR pipeline rewrites it down to penguin.py text. There is no registry: hilo::registerMHLOPasses @ 0x1ee12f0 is a flat pm.addPass(...) spine, and the linear source order is the pipeline order. The StableHLO fork (hilo::registerStableHLOPasses @ 0x1ee2120, selected by CompileConfig byte [+0x1CA]≠0) is the same spine with 5 extra insertions — 32 → 37 steps. Every step except the terminal emitter is gated on a CompileConfig byte (default-off unless a cl::opt flips it; the lone default-on is step 6 LowerComplex, set by a static initializer).
The full ordered MHLO spine is the canonical listing in 4.32. Index of the 32 steps by family:
| # | MHLO step (create…Pass) | Family / documenting page | Gate | Conf |
|---|---|---|---|---|
| 1 | Canonicalizer | upstream MLIR canonicalize | cfg[0x119] | CONFIRMED |
| 2 | NeuronControlDepTupleSimplifier | controldep-tuple-flatten-mlir | cfg[0x200] | CONFIRMED |
| 3 | StableHLOCollectiveBroadcastToAllGather | collective bcast→all_gather | uncond | CONFIRMED |
| 4 | VerifySupportedOps | op-legality verifier | cfg[0x136] | CONFIRMED |
| 5 | CanonicalizeConv | conv-canonicalization | cfg[0x12F] | CONFIRMED |
| 6–7 | LowerComplex / LowerComplexExtra | complex→real | cfg[0x11A](on) / [0x11B] | CONFIRMED |
| 8 | RemoveOptimizationBarriers | strip optimization_barrier | cfg[0x11C] | CONFIRMED |
| 9–10 | IdentifyCrossPassTensors / Rematerialize | cross-pass tag + recompute | cfg[0x116] | CONFIRMED |
| 11 | CoalesceCollectiveOps | MLIR collective coalescing | cfg[0x117] | CONFIRMED |
| 12 | ConvertFSPatternToCustomCalls | FS subgraph → AwsFSPattern5 | cfg[0x11F] | CONFIRMED |
| 13 | RemoveDeadValues | upstream MLIR DCE | uncond | CONFIRMED |
| 14 | NeuronInstCombine | neuron-instcombine-mlir | uncond | CONFIRMED |
| 15 | NeuronOpFusion (6 sub-passes) | op-fusion-dot-elementwise, rmsnorm-fusion-cluster-codegen | cfg[0x120] | CONFIRMED |
| 16 | FoldIota | pow(iota)→const | cfg[0x118] | CONFIRMED |
| 17–18 | SchedulePostorder / AnalyzeSchedule | schedule-fusion-composite | cfg[0x130]/[0x134] | CONFIRMED |
| 19 | ReplaceTokenTypeWithU8 | !mhlo.token→tensor<ui8> | uncond | CONFIRMED |
| 20 | ScatterMotion | scatter code-motion | uncond | CONFIRMED |
| 21 | ScheduleFusion | schedule-fusion-composite | cfg[0x135] | CONFIRMED |
| 22–23 | HoistCompute / MemcastMotion | hoist / late-cast motion | cfg[0xE9]/[0xE5] | CONFIRMED |
| 24 | PruneFunctions | dead-function elim | uncond | CONFIRMED |
| 25 | SixtyFourHack (prepended before 26) | i64→i32 emulation | qword_9C71338==0 | STRONG |
| 26 | PenguinizeIO | stablehlo-printer-penguinize | uncond | CONFIRMED |
| 27 | CanonicalizeForTensorizer (8 sub-rewriters) | canonicalize-for-tensorizer | uncond | CONFIRMED |
| 28 | TensorizerLegalization | tensorizer-legalization | uncond | CONFIRMED |
| 29–30 | LegalizeAlias / VerifyAliasing | insert AliasingCopy + RAW check | uncond / cfg[0x13C] | CONFIRMED |
| 31 | MLIRInstructionHistogram | op-count diagnostics | uncond | CONFIRMED |
| 32 | MhloToPyPenguin (terminal) | mhlo-to-python-printer-driver, -heavy | uncond | CONFIRMED |
The 5 StableHLO-only insertions (32 → 37)
The StableHLO spine twins every MHLO step and adds 5 of its own (4.32):
| After step | StableHLO-only insertion | Role | Conf |
|---|---|---|---|
| 1 | HloLegalizeToStablehlo | mhlo → stablehlo bridge | CONFIRMED |
| 1 | ConvertCustomCallToAllReduce | custom_call("mhlo.all_reduce") → all_reduce | CONFIRMED |
| 14 | FusionToComposite | mhlo.fusion → stablehlo.composite | CONFIRMED |
| 26 | LegalizeSRA | shift_right_arithmetic signedness | CONFIRMED |
| 26 | LegalizeScatter | stablehlo.scatter → F32 + canonical body | CONFIRMED |
QUIRK — step 25 is prepended, not appended.
SixtyFourHack's gate (jz→altblk @0x1ee19a0, on globalqword_9C71338==0) inserts it before step 26PenguinizeIO, so it runs ahead of IO packaging despite appearing 25th in the source. A reimplementer whoaddPass-es it in textual position sequences it wrong. (STRONG — disasm-only control flow.)
3. Stage 3 — Penguin middle-end (248 modules, run-list ~varies)
The Penguin middle-end is not a registry and not a flat pipeline — it is a catalog of Cython pass modules sequenced at run time by generator functions. Four directories partition the catalog; counts are ls-verified (excluding __init__):
| Directory | Modules | Scope | Documenting page |
|---|---|---|---|
penguin/transforms/ | 71 | target-independent IR passes (DCE, VN, LICM, simplify, delinearize, predicate) | 5.7 |
penguin/targets/transforms/ | 131 | target-oriented, shared Sunda+Tonga (alloc/spill, layout, tiling, collective, DMA, type-legalize, Tritium fusion) | 5.7 |
penguin/targets/sunda/passes/ | 6 | Sunda-specific ISel / tiling | 5.7 |
penguin/targets/tonga/passes/ | 40 | Tonga-specific ISel / tiling / scheduler | 5.7 |
| Total | 248 | (targets/cayman/passes/, targets/core_v4/passes/ ship only __init__ — reuse Sunda/Tonga) |
The targets/transforms/autotune/ subpackage (6 modules: Autotuner _Compiler _PerformanceMetric _Search _TreeSearch _TreeSearchVisualizer) is counted separately, not in the 131.
GOTCHA — module count ≠ pass count. ~8–10 modules in the two
transforms/dirs export noPass/DotTransformsubclass — they are helper libraries (DataflowUtilInstTransformUtilsIPUtilsLoopTransformUtilsTensorContractUtilsTensorOpUtilsInstBuilderIntrinsicBuilderDataflowUtils). The real pass-class set is the subset whose top-level class subclassesDotTransformorBaseAnalysis. The 248 is the verifiable module anchor; the pass-class subset is a few smaller. (STRONG — by-class filtering not exhaustively enumerated.)
Run order — the driver, not the directory
There is no static order in the directory listing. The order is set by the four SharedCodeGenFlow generators (peephole_optimizations, legalize_pe_insts, nki_codegen, codegen_optimization_post_tritium_fusion), each yielding PassType specs that a PassConstructorBuilder folds. The canonical post-fusion list (with its required/optional qualifiers and the spill-vectorize-respill double-FastSpillGeneration) is in 5.7. Index of the high-population families:
| Family | Representative passes | Documenting page | Conf |
|---|---|---|---|
| Alloc / spill | AllocateBlocks MaxLiveSpiller FastSpillGeneration StackAllocator SpillPSum | scheduling-minreg, tensor-buffer-node | CONFIRMED |
| Layout | LayoutTilingPipeline PAGLayout* LayoutPreprocessing NKIKernelLayout | layout-tiling-pipeline, layout-middle-end | CONFIRMED |
| Tiling / vectorize | FlattenAxesForTiling VectorizeLoop SFKVectorizer LoopSplitting PG*Analysis | loop-transform-clients | CONFIRMED |
| Loop transforms | LICM LoopFusion PerfectLoopNest FlattenLoop Delinearization | loop-transform-clients | CONFIRMED |
| ISL / affine | IslSimplifier-family, ModDivDelinear, AffinePredicateResolution | isl-simplifier, isl-codegen, affine-expr-algebra | STRONG |
| Collective (SPMD/CC) | CCOpFusion CoalesceCCOp TileCCOps SPMDCodeGen SimpleAllReduceTiling | data-movement-fusion | CONFIRMED |
| DMA | DMALegalizer DMALocalityOpt DataStreaming DramToDramTranspose | dge-level-dynamic-dma, tensorcopy-dynamic-generators | CONFIRMED |
| Software pipelining | SoftwarePipelineCodeGen | software-pipelining | CONFIRMED |
| Tritium fusion (+autotune) | TritiumFusion TritiumFusionBase, autotune/Autotuner | 5.7 autotuner | CONFIRMED |
| ISel (per-target) | SundaISel (sunda), TongaISel (tonga) | 5.7 | CONFIRMED |
| Codegen / emit | NkiCodegenPass, BirCodeGenLoop, targets/codegen/* | ir-mlir-bir-mapping | CONFIRMED |
QUIRK — a pass can appear twice in the run-list.
FastSpillGenerationruns before and afterSFKVectorizer(vectorization creates new live ranges to spill);nki_codegenis chained into the post-fusion list. Aset-based reimplementation that de-dups specs by class silently drops the second spill. The Penguin run-list length is therefore not a function of the module count — it is the generator's yield sequence, with repeats. (CONFIRMED membership; STRONG order — version-counter source-order trace.)
4. Stage 4 — walrus backend (150 names → 121 classes)
The walrus backend is a GeneratorRegistration registry: 150 register_generator_<name>__ static initializers each install a name → factory entry, but they construct only 121 distinct C++ pass classes — 10 classes are registered under multiple names, parameterized at construction by a memory space, optimization level, or scheduling phase. The pipeline schedules these into ~180 steps (some names at several positions, plus interposed !isRealPass check/dump/sim passes).
- 150 CONFIRMED on the binary:
nm -DC libwalrus.so | rg -o 'register_generator_[a-z0-9_]+' | sort -u | wc -l= 150. - 121 STRONG (derived): count of distinct
_M_invokector targets over the 150 bodies. The 10 multi-registered groups contribute 29 surplus names (9+7+3+2+2+2+1+1+1+1);121 + 29 = 150.
The full 150-name → class → granularity → evidence table is the canonical listing in 8.1 §"The full 150-name table". The 150→121 collapse must be represented, not flattened — here are the 10 multi-registered classes that produce the gap:
| Class | Names | Surplus | Discriminator | Conf |
|---|---|---|---|---|
MemoryAnalysis | 10 | 9 | which prior pass the snapshot follows (post-rotation/coloring/dma/sched/unroll) | CONFIRMED |
ColoringAllocator | 8 | 7 | Type ∈ {SB,PSUM,REG,DRAM,DRAM-shared} + post_lnk/debug | CONFIRMED |
AddressRotation | 4 | 3 | space dram/psum/sb + post_schedule | CONFIRMED |
DMAOptimization | 3 | 2 | psum/sb/input-coalescing | CONFIRMED |
FullUnroll | 3 | 2 | unrollLevel ∈ {all,some} + memloc-generation | CONFIRMED |
SeparateLoadAndCompute | 3 | 2 | base / with_memset / post_ada | CONFIRMED |
AntiDependencyAnalyzer | 2 | 1 | base / post_shared_dram | CONFIRMED |
DeadCodeElim | 2 | 1 | optlevel o0 / o1 | CONFIRMED |
PerfSimPass | 2 | 1 | perf_sim / perf_sim_at_end | CONFIRMED |
PrefetchScheudling (sic — misspelled in binary) | 2 | 1 | before_sched / after_sched | CONFIRMED |
The other 111 names are 1:1 with their class. Index of the 150 names by family, pointing each at the documenting 8.x page:
| Family | Representative names | Documenting page | Conf |
|---|---|---|---|
| Pass hierarchy / registry | (the BackendPass base, forks, GeneratorRegistration) | 8.1 | CONFIRMED |
| Optlevel pipeline | (the optlevel builders that call addPass("<name>")) | pass-pipeline-optlevels | CONFIRMED |
| NKI-AST→BIR / unroll | translate_nki_ast_to_bir unroll full_unroll_* heuristic_unroll flatten_small_loops | translate-nki-unroll | CONFIRMED |
| DMA legalization | legalize_strided_dma legalize_cce_dma lower_generic_indirect lower_dynamic_dma | dma-legalization | CONFIRMED |
| DMA materialization / queues | dynamic_dma_setup dynamic_dma_scan alloc_queues insert_dma_switch_queue_instance optimize_queue_switch | dma-materialization, dma-queues | CONFIRMED |
| DMA engine binding | assign_hwdge_engine assign_trigger_engine infer_stream_ids label_dma_qos | dma-engine-binding | CONFIRMED |
| DMA metrics / profiler | dma_metrics dma_optimization_psum dma_optimization_sb input_dma_coalescing | dmametrics-profiler, alt-allocators-dma-opt | CONFIRMED |
| lower_select / control / branch | lower_select lower_control lower_branch | lower-select-control-branch | CONFIRMED |
| Engine-lowering set | lower_sync lower_act lower_dve lower_ap lower_ac lower_dma lower_symbolic_inst lower_local_collectives | engine-lowering-set | CONFIRMED |
| Coloring / DRAM / PSUM alloc | coloring_allocator_* (8) coloring_allocator_with_loop linear_scan_allocator psum_legalization | allocator-drivers, dram-allocator, psum-allocator | CONFIRMED |
| Address rotation | address_rotation_{dram,psum,sb} address_rotation_psum_post_schedule | address-rotation | CONFIRMED |
| Memory analysis (10 snapshots) | memory_analysis_after_* | allocator-drivers | CONFIRMED |
| Scheduling | pre_sched post_sched prefetch_scheduling_{before,after}_sched instruction_reorder | post-sched-schedulers | CONFIRMED |
| Dependence graph / dep-opt | build_fdeps dep_opt dep_reduction order_constraints anti_dependency_analyzer* | dependence-graph, dep-opt-reduction | CONFIRMED |
| Peephole / constprop / remat | peephole_opts early_peephole_opts constant_propagate remat_optimization remove_redundancies seq_inst_opt | peephole-constprop-remat | CONFIRMED |
| Matmul ordering / acc-groups | order_column_tiled_mms legalize_mm_accumulation_groups | matmul-ordering-accgroups | CONFIRMED |
| Loop-opt (backend) | loop_optimization | loopopt-licm-fusion, loopopt-transforms | CONFIRMED |
| Value numbering / mem2reg | value_numbering vn_splitter mem2reg non_ssa_legalization | legality-dispatch | STRONG |
| LNC splitter / barrier | lnc_splitter lnc_barriercheck lnc_verifier shared_mem_cb_insertion | lnc-splitter, barriercheck | CONFIRMED |
| Local collectives | lower_local_collectives coalesce_multichannel_cc_ops sync_before_global_cc | local-collectives | CONFIRMED |
| BIR linker / kernel inline | bir_linker inline_bir_kernel inline_nki_kernel memreserve runtime_memory_reservation | bir-linker, memreserve-kernel-inline | CONFIRMED |
| Codegen / bin emission | codegen neff_packager | codegen-driver, bin-emission | CONFIRMED |
| Verifiers / serdes | birverifier bir_racecheck verify_bir_serdes oom_checker | birverifier-per-op | CONFIRMED |
Perf-sim / metrics (!isRealPass) | perf_sim perf_sim_at_end perf_sim_package_pass report_stats dumper hasher | perfsim-cost-model, perf-sim-wiring, metricstore, parserdumper | CONFIRMED |
GOTCHA —
serial*is not "always serial". In 8.1's full table the granularity column shows a Fork tag only where an explicitadd*ParallelPass<Class>template instance exists;serial*means "added by name (default serial child)" — but the same class may be fork-wrapped at a different call-site, because granularity is a property of the call-site, not the class. Do not readserial*as a guarantee.
5. Adversarial Self-Verification
The cross-stage counts that this catalog turns on, each re-challenged directly against the cp310 binaries:
- Stage 1 = 112.
objdump -d --start-address=0x1e72270 --stop-address=0x1e744b0 hlo-opt | rg -c 'call.*1ebc3f0'→ 112 (calls toRegisterHloPass). One name per call, key =pass->name(). CONFIRMED on the binary. - Stage 2 = 32 MHLO + 5 = 37 StableHLO.
registerMHLOPasses@0x1ee12f0(3096 B) is a flat 32-stepaddPassspine;registerStableHLOPasses@0x1ee2120(3142 B) is the twin + 5 insertions. The 5 inserts (HloLegalizeToStablehlo,ConvertCustomCallToAllReduce,FusionToComposite,LegalizeSRA,LegalizeScatter) are CONFIRMED in 4.32. Step count CONFIRMED; theSixtyFourHackprepend (step 25) is STRONG (disasm-only). - Stage 3 = 248 modules (71/131/6/40).
ls <dir>/*.so | grep -v __init__ | wc -lin each of the four directories → 71, 131, 6, 40 (sum 248).targets/transforms/autotune/= 6 (separate).targets/cayman/passes/andtargets/core_v4/passes/contain only__init__. CONFIRMED on the binary (module count; pass-class subset is a few smaller — helper libs, flagged in §3). - Stage 4 = 150 names → 121 classes.
nm -DC libwalrus.so | rg -o 'register_generator_[a-z0-9_]+' | sort -u | wc -l→ 150 (CONFIRMED on the binary). The 10 multi-registered groups (MemoryAnalysis=10,ColoringAllocator=8,AddressRotation=4,DMAOptimization/FullUnroll/SeparateLoadAndCompute=3 each, four ×2) sum to 29 surplus names;121 + 29 = 150. 150 CONFIRMED; 121 STRONG (distinct-ctor-target count over the verified 8.1 table, not independently grep-able). - The four name→pass mechanisms are genuinely different. Stage 1 =
llvm::StringMapkeyed byname()read-back; Stage 2 = imperativeaddPasswith no name table; Stage 3 =PassTypespecs folded byPassConstructorBuilder, no name table; Stage 4 =_Hashtablekeyed by the literalregisterGeneratorstring. Each is documented and symbol-anchored in its normative page (4.1, 4.32, 5.7, 8.1). CONFIRMED.
No pass name on this page is fabricated: every name is the verbatim string carried by its normative source page, which in turn read it from the binary (name() literal, create…Pass factory symbol, __pyx_n_s_ interned token, or register_generator_*__ symbol). Where this catalog points a family at a documenting wiki page, the slug was confirmed present on disk; families with no dedicated detail page point at their stage's normative registry page. The libBIR/libwalrus binaries and their IDA databases are present in-corpus — backend class addresses cited via 8.1 are CONFIRMED, not inferred.
NOTE — what this page is not. It is an index, not a replacement for the four normative tables. The per-row name→class→vtable→entry detail for Stage 1 lives in 4.1 §2; the per-step MLIR spine in 4.32; the Penguin driver order in 5.7; and the full 150-name → class → granularity table in 8.1. This catalog reconciles their counts and gives one map across all four.
Related Components
| Stage page | Relationship |
|---|---|
| 4.1 — hlo-opt Pass Registry | The 112-name --passes registry; source of §1 |
| 4.32 — hlo2penguin MLIR Pipeline | The 32+5-step MLIR spine; source of §2 |
| 5.7 — Penguin Pass Roster & Pipeline Driver | The 248-module catalog + SharedCodeGenFlow order; source of §3 |
| 8.1 — BackendPass Hierarchy & 150→121 Registry | The 150-name walrus registry; source of §4 |
Cross-References
- The hlo-opt Pass Registry (the
--passesTable) — Stage 1, the 112-row canonical table this catalog indexes - hlo2penguin MLIR Pipeline Order & Entry Flow — Stage 2, the imperative
addPassMLIR spine - Penguin Pass Roster & Pipeline Driver — Stage 3, the Cython module catalog and
OptLevelgate - BackendPass Hierarchy & the 150-Name→121-Class Registry — Stage 4, the walrus
GeneratorRegistrationregistry - The walrus Pass Pipeline & Optlevel Planes — how the 150 walrus names are scheduled per
-Olevel - The Opt-Level Planes — -O0..-O3 — the
--optleveldial that gates Stage 3 and Stage 4 selection - walrus_driver Backend CLI & Pass Vocabulary — the
--passsurface that drives the Stage 4 registry - Master Opcode Reference · Master Dtype / Enum Reference — the sibling Part-14 reference catalogs