Terms as used in neuronx_cc 2.24. Where a name is the compiler's own (a symbol, a module, a codename), that is noted; where it is this book's shorthand, that is noted too.
The Neuron stack carries a dense, partly-internal vocabulary: a single data structure may be called one thing in a Python module, another in a C++ symbol, and a third in an error string. This page is the dictionary. It also fixes the naming conventions the rest of the book follows, so that "BIR", "Penguin", "KLR", and "the engines" mean exactly one thing throughout.
XLA's High-Level Optimizer IR — the HloModule protobuf that enters from PyTorch-XLA / JAX.
MHLO / StableHLO / CHLO
The MLIR dialects hlo2penguin ingests; StableHLO is the portable form, MHLO the in-memory XLA dialect, CHLO the "client" high-level ops.
Penguin IR
The mid-level, tile-and-loop SSA representation optimized by the middle-end. A Python object graph backed by Cython modules under starfish/penguin/. The internal codename for the tensorizer/mid-level layer.
Tensorizer
The transform layer that tiles tensor ops into loop nests over hardware tiles; the source of names like CanonicalizeForTensorizer.
BIR
Backend IR (libBIR.so, bir::*). One bir::Instruction per Tonga hardware instruction; a 110-entry opcode enum. The level walrus operates on and the JSON wire format serializes.
KLR
The "KLIR"/beta2 intermediate carried between the NKI tracer and the backend, lowered by KlirToBirCodegen. Retained but dormant for internal re-trace in this build (the live path is beta3).
NEFF
Neuron Executable File Format — the compiler's output container. A gzip-wrapped PAX tar of JSON + per-engine .bin members; not an ELF.
kelf
A TVM/nnvm graph_runtime-dialect JSON (kelf-N.json) embedded in the NEFF describing a subgraph.
Tensor Processing Block — the NeuronCore compute complex containing the engines.
PE
The Processing Element array — the systolic matmul engine.
Pool
The pooling/reduction engine. GPSIMD is an external alias of Pool (see below).
Activation (Act)
The activation engine; evaluates PWP functions via on-chip LUTs loaded by LoadActFuncSet.
DVE
The vector/data engine, driven by an on-device microcode table.
SP
The control processor — the TPB's sequencer; runs register-lane ops, branches, sync.
GPSIMD
Two distinct things sharing a name: (1) the external alias of the internal Pool engine, surfaced as InstGPSIMDSB2SB (cross-core SB-to-SB); (2) the 8-core Xtensa custom-op CPU cluster that runs user custom ops. They are unrelated units; see 11.9.
SBUF
State Buffer — the on-core scratchpad SRAM; replicated per logical neuron core.
PSUM
Partial-Sum buffer — the matmul accumulator banks; replicated per core.
DRAM / HBM
Off-core high-bandwidth memory; partitioned across logical cores (contrast SBUF/PSUM).
LNC
Logical NeuronCore — the multi-core split of a physical NeuronCore; the backend splits the BIR graph across LNCs (lnc_splitter) and re-links per-core streams (bir_linker).
VNC
The cross-core link layer (vnc_remote_addr_map, vnc_link) that wires LNC cores together.
DGE
Dynamic Generation Engine — the descriptor-generation level for dynamic-offset DMA.
OCP Microscaling — the block-scaled low-precision format (E8M0 per-block scale over FP8 elements). The only low-precision quantize that reaches silicon.
E8M0
The 8-bit exponent-only block-scale type used by MX.
RNE
Round-to-nearest-even — the device rounding mode everywhere (there is no stochastic rounding in this build).
x4-packing
The 4-elements-per-word packing of sub-byte dtypes in BIR's dtype model.
golden
The reference (CPU oracle) numeric path, via xla_infergoldens / oneDNN; distinct from the device path (e.g. int8 quantize is golden-only).