Collective-Type + cc_op Enum Reference

This is the enum-consolidation page for the GPSIMD collective-communication subsystem — the single authoritative cross-reference that every collective op page links back to. It pins, byte-exact, the complete enum set spread across two layers of the stack:

• the on-instruction ISA enums baked into the TPB instruction word and read verbatim from the shipped Cadence Vision-Q7 (ncore2gp) ISA headers (aws-neuronx-gpsimd-customop-lib 0.21.2.0, the four per-arch copies neuron_{sunda(v2),cayman(v3),mariana(v4),maverick(v5)}_arch_isa/tpb/), and
• the host-runtime encoder enums carried in libnrt.so (NRT, the host process that lowers the pseudo-ops), re-extracted directly from that binary's DWARF (.debug_info, BuildID 8bb57aba0fb2e0035f1d88e9fc4fb3e7387c102e).

The collective subsystem is unusual in that the same logical operation set is described by four different "kind" vocabularies at four layers (ISA COLLECTIVE_TYPE, host enc_op_type, host/public nrt_op_type, firmware cc_op), and the reduce arithmetic is described by three separate packed enums at three fold scopes (REDUCE_OP, CCE_OP/SDMA_CCETYPE, DGE_COMPUTE_OP). The bulk of this page is reconciling those parallel vocabularies, because conflating their ordinals is the single most common re-implementation error — they agree on operation names but disagree on values.

Every value below is anchored to its defining symbol and file:line (ISA headers) or DWARF DIE offset (libnrt.so). Confidence is tagged HIGH/MED/LOW × OBSERVED/INFERRED/CARRIED.

Source-of-truth contract. The committed op pages (trigger-collective, trigger-collective2-ext, all-reduce, s3d3-collective, sendrecv, …) cite the enum values from here. Where a committed page and the binary disagree, this page carries a CORRECTION callout and the binary wins.

1. The collective opcode space

The enums on this page ride a fixed family of TPB opcodes. Two are real hardware instructions (the cross-lane compute-reduce and the SB2SB iDMA leg); the rest are pseudo-ops that NRT lowers host-side. The pseudo-op class rule is verbatim in common.h: an opcode is a pseudo-op iff its upper three bits are 0b110 (0xC0..0xDF) — "generated by compiler and translated into non-pseudo HW instructions by NRT". None of the 0xC*/0xD* collective ops execute on hardware; NRT decomposes them into SB2SB_COLLECTIVE (0xBF) + DMA + EVENT_SEMAPHORE (0xA0) legs.

[HIGH/OBSERVED — every ordinal read from the cayman common.h OPCODE enum + instruction_mapping.json.] The RDMA gather variants (rdma-gather-pseudo-ops) reuse 0xC8/0xD9 with their own ctype/alg field values.

2. ISA collective enums (carried in the instruction word)

All bodies are verbatim from the cayman (v3) headers. The underlying type is the 1-byte NEURON_ISA_PACKED enum unless noted. Cross-arch identity is in §10.

2.1 NEURON_ISA_TPB_COLLECTIVE_TYPE (ctype) — common.h:792, 1 B

The "which collective" kind carried by 0xC8 (offset 32) and 0xD9 (offset 14); fixed to ALL_REDUCE for the dedicated 0xC7. 10 enumerators, 0x0..0x9.

[HIGH/OBSERVED — full body @common.h:792-803.]

2.2 NEURON_ISA_TPB_COLLECTIVE_DIMENSION (cc_dim) — trigger_collective2.h:27, 1 B

New in v2 (0xD9 offset 15): which SBUF dimension the collective acts along. DIM_0 = 0x0, DIM_1 = 0x1. The host validator strings (libnrt .rodata, OBSERVED) read "%d rank cc_dim 0 sb2sb expectes input is distributed to ranks in free dimension" and "Collective instruction: does not support cc_dim 0/1 for this op %d" → DIM_0 selects the FREE dimension, DIM_1 the PARTITION dimension; not all ctypes accept both. [field+values HIGH/OBSERVED; DIM_0=free reading MED from the "free dimension" wording.]

2.3 NEURON_ISA_TPB_LNC_SIZE_FMT (lnc_size_fmt) — common.h:815, 1 B

Header comment: "LncSize setting for sb2sb collective using q7 iDMA". The peer/die grouping for SB2SB (0xBF offset 32) and the participant model for CORE_BARRIER (a VNC = an LNC-grouped pcore set).

GOTCHA — SB2SB rejects LNC4/LNC8. SB2SB is an intra-node, ≤2-NC operation (LNC1 self / LNC2 pair). The host string "We do not support a SB2SB for multi-node workloads" (OBSERVED) confirms LNC4/LNC8 are rejected on the SB2SB leg even though they are legal enum members. [enum HIGH/OBSERVED @common.h:815-820.]

The committed pages cite the grouping as LNC1=0 / LNC2=1 / LNC4=2 / LNC8=3 — this matches the header exactly.

2.4 The collective2-_ext enums — trigger_collective2_ext.h

These four enums ride the 0xDA PSEUDO_EXTENSION struct. Note the headers double-prefix the enumerator names (e.g. NEURON_ISA_TPB_INSTR_CHAINING_INSTR_CHAINING_NONE).

INSTR_CHAINING ties to the firmware cc_op.trigger_next bit (§7). [all HIGH/OBSERVED.]

2.5 NEURON_ISA_TPB_DMA_CONFIGS — common.h:713, 1 B packed struct (ext off 41)

Not an enum — the DMA QoS priority carrier on the _ext struct:

typedef struct NEURON_ISA_TPB_DMA_CONFIGS {        // common.h:713
    uint8_t priority_class    : 3;   // DMA QoS priority class 0..7
    uint8_t reserved_bitfield : 5;   // must be zero
} NEURON_ISA_PACKED NEURON_ISA_TPB_DMA_CONFIGS;

[HIGH/OBSERVED.]

2.6 NEURON_ISA_TPB_DTYPE (op/leg element dtype) — common.h:722, 4-bit packed

The Rosetta dtype that passes verbatim to the SDMA descriptor (== SDMA_DTYPE == nrt_dtype, §5.3). Values (header is in name order; tabulated here by ordinal):

Header notes: INVALID "used in RTL for bitvec"; FP32 "RTL will use 0xB for FP22 partial fp32 type" (this 0xB overlap surfaces as the RESERVED alias in SDMA_DTYPE, §5.3). [HIGH/OBSERVED @common.h:722-739.]

3. Host runtime collective enums (libnrt.so DWARF)

All bodies below were re-extracted directly from libnrt.so's DWARF this pass (objdump --dwarf=info; DW_TAG_enumeration_type → DW_TAG_enumerator → DW_AT_const_value). Underlying type is a 4-byte enum. The DIE offset is given for each so the extraction is re-runnable.

3.1 enc_op_type — the cc_op KIND in the host encoder (DIE <0x3bbd0>)

The host re-encoding of ctype plus the host-only decomposition kinds. 13 real op kinds (0..12) with two value-13 sentinels.

NOTE. ENC_OP_INVALID and ENC_OP_N are both ordinal 13 (two DW_AT_const_value : 13 enumerators in the same DIE), confirming exactly 13 real op kinds (0..12). This matches sendrecv.md (ENC_SEND=5, ENC_RECV=6) and trigger-collective2-ext.md (ENC_PERMUTE_IMPLICIT=10 … ENC_ALLTOALL_V=12, ENC_OP_INVALID=13) byte-for-byte. [HIGH/OBSERVED.]

3.2 enc_comm_type — topology SCOPE (DIE <0x34a15>)

H_COMM_INTRA_ID = 0, H_COMM_INTER_ID = 1, H_COMM_MAX_ID = 2 (count). INTRA = within a node/die-group; INTER = across nodes/dies. A hierarchical all-reduce runs both an INTRA leg and an INTER leg (§8 legality). [HIGH/OBSERVED.]

3.3 enc_alg_type — the algorithm selector (DIE <0x61eb3>)

11 real algorithms (0..10) + INVALID=11. All 0..10 fit the firmware's 4-bit algo_type nibble (§7).

This matches trigger-collective2-ext.md's …ENC_ALG_BW_OPT_MESH=10 ENC_ALG_INVALID=11 exactly. [HIGH/OBSERVED.]

3.4 enc_alg_mesh_type — mesh sub-type / firmware algo_sub_type (DIE <0x125d7c>)

ENC_ALG_FULL_MESH=0, ENC_ALG_GROUPED_MESH=1, ENC_ALG_MESH_TRN2=2, ENC_ALG_MESH_SWITCH=3, ENC_ALG_MESH_INVALID=4. 4 real sub-kinds (0..3), all fit the firmware's 3-bit algo_sub_type. [HIGH/OBSERVED.]

3.5 reduction_type_t — the ring read/write fold PATTERN (typedef → DIE <0x60c99b>)

This is a ring access pattern, not the reduce op. It is the 3rd argument of enc_primitive::recv_reduce_*(enc_half_chunk_index, SDMA_CCETYPE, reduction_type_t, …) and direct_reduce_send_*.

NOTE — do not confuse with the reduce op. reduction_type_t selects the descriptor read/write rendezvous shape of the ring step; the actual add/max/min is the separate SDMA_CCETYPE argument that sits beside it in the same signature. This matches the all-reduce.md callout exactly. [HIGH/OBSERVED — DW_AT_const_value 0/1/2 read from DIEs <0x60c99c>/<0x60c9a2>/<0x60c9a8>.]

CORRECTION — argument position. SX-CCL-11 §3.5 described reduction_type_t as the "2nd argument" of recv_reduce_*. The demangled libnrt signature is recv_reduce_send(enc_half_chunk_index, SDMA_CCETYPE, reduction_type_t, bool, bool) (@0x16ad70), so it is the 3rd argument (SDMA_CCETYPE is 2nd). all-reduce.md already states "3rd argument" — that page is correct; the sibling report's "2nd" is off by one. [HIGH/OBSERVED.]

3.6 enc_mesh_event_type — the mesh event-tape event kinds (DIE <0x34a50>)

The mesh-variant "event tape" event kinds. SX-CCL-11 pinned only the first 7; the full 61-enumerator body was recovered this pass. The enum is partitioned by algorithm phase via named sentinels (ENC_*_NUM_EVENT_START / ENC_*_NUM_EVENT_TYPE), which alias the first/last ordinal of each phase block — this is the per-algorithm event-window layout the mesh sema overlay (§7) indexes into.

The EVT_FUNCTION_BARRIER_FIRST_COLL / _LAST_COLL events tie to the NCFW function-barrier. [HIGH/OBSERVED — all 61 DW_AT_const_value read this pass; the phase-start aliases (=8, =14, =23, =53) confirm the 4-phase partitioning.]

3.7 encd_neigh — the SB2SB peer selector (DIE <0x3a703>)

The host analogue of the device lnc_size_fmt peer grouping.

[HIGH/OBSERVED — ordinals read this pass; INVALID/NUM both const_value 8.]

4. The op-kind cross-map (ctype ↔ enc_op_type)

The on-instruction COLLECTIVE_TYPE (ctype) is RE-ENCODED by the host into enc_op_type; the ordinals DIFFER — do not conflate. The host nrt_collectives encoder builds enc_op_type from ctype plus the host-only decomposition kinds.

SEND/RECV (enc 5/6) are carried by the dedicated 0xCB (sendrecv: peer_id u64 @16, is_send u8 @24); BROADCAST/REDUCE (enc 2/3) are internal decomposition legs of the larger collectives. [name-correspondence HIGH; the ctype→enc_op_type numeric remap is MED — ordinals OBSERVED on both sides, no byte-level remap table dumped.]

5. The reduce-op layers and the dtype pass-through

5.1 The three reduce-op layers (the core deliverable)

There are three distinct reduce-op enums (plus a fourth DMA-generation compute enum), at three different fold scopes. They are separate packed types that do NOT share an encoding — they agree only on operation names; the per-element add/max/min math is the same ground-truth primitive everywhere.

COMPUTE semantics (verbatim header): ADD/AVERAGE/MAX are fp32 math; OR/AND/XOR are raw u8/u16/u32 with no fp32 conversion; AVERAGE multiplies each element by the scale f32 field then adds. The compute reduce also carries NEURON_ISA_TPB_REDUCE_AXIS (s4d4_cr.h:71): ALL=0 (reduce all dims → single value), PARTITIONS=1 (reduce only across SBUF/PSUM partitions).

The host-side public reduce op is nrt_op_type (libnrt DWARF <0xd8fa>): NRT_OP_ADD=0 NRT_OP_FMA=1 NRT_OP_MAX=2 NRT_OP_MIN=3 NRT_OP_INVALID=15 — taken by nrt_cc_prepare and translated to SDMA_CCETYPE value-preservingly for {ADD,FMA,MAX,MIN} (translate_op_type is identity; only the invalid op hits the __assert_fail cold tail @0x7f5b0).

5.2 Membership logic — why three+one enums, where each is used

The four enums sit at fold scopes that compose innermost → outermost, plus one side path. Reproduced as annotated pseudocode naming the real symbols:

// Innermost: fold the SIMD lanes of ONE vector register to a scalar.
//   opcode 0x7C/0x7D, struct S4D4_CR, on the POOL engine.
scalar = CrossLaneReduce(vector, NEURON_ISA_TPB_REDUCE_OP op,   // ADD/AVG/MAX/OR/AND/XOR
                                 NEURON_ISA_TPB_REDUCE_AXIS ax); // ALL | PARTITIONS

// Outermost (collective): fold across BUFFERS / CORES on the SDMA engine.
//   the ring/mesh/hier reduce-scatter & all-reduce legs.
//   The host carries SDMA_CCETYPE; only {ADD,MAX,MIN} reach the HW descriptor,
//   whose field is the ISA CCE_OP {0,2,3} byte-subset.
status = enc_primitive::recv_reduce_send(enc_half_chunk_index chunk,
                                         SDMA_CCETYPE   cce,   // ADD0/FMA1/MAX2/MIN3/EXT4/GCE5
                                         reduction_type_t pat, // §3.5 ring shape, NOT the op
                                         bool, bool);
//   CCE descriptor field <- (uint8_t) cce, but only ADD0/MAX2/MIN3 (== CCE_OP) ever
//   reach hardware; FMA1/EXT4/GCE5 are host-runtime-only carrier modes.

// Side path: DMA-generation engine compute-on-copy (reduction-add DMA).
//   B = op(A, B) during the copy; NONE == pure memcpy. DISTINCT from CCE_OP.
dge_copy(dst /*B*/, src /*A*/, NEURON_ISA_TPB_DGE_COMPUTE_OP op); // NONE0/ADD1/MUL2/MAX3/MIN4

The collective op KIND (enc_op_type, §3.1) is a third, orthogonal axis — it is the operation (all-reduce vs reduce-scatter) that parameterizes the legs with one of these reduce ops; it is not itself a reduce op.

GOTCHA — the alignment islands. REDUCE_OP and CCE_OP/SDMA_CCETYPE agree on ADD=0 and MAX=2 but disagree on slot 1 (REDUCE_OP AVERAGE=1 vs SDMA FMA=1) and slot 3 (REDUCE_OP BITWISE_OR=3 vs SDMA MIN=3). They are not interchangeable. DGE_COMPUTE_OP is NONE-based, so its ADD=1/MAX=3/MIN=4 align with nothing. A reimplementation that copies a REDUCE_OP value into an SDMA CCE descriptor will silently compute MIN where it meant BITWISE_OR. [reconciliation HIGH — every body OBSERVED.]

The ISA ALU_OP (common.h:939) is the full ALU enum; the collective in-DMA reduce path uses only its ADD=0x04 / MAX=0x08 / MIN=0x09 members as the op field that trigger-collective then maps to CCE_OP/DGE_COMPUTE_OP.

Why two DMA reduce vocabularies (CCE_OP vs SDMA_CCETYPE). CCE_OP is the hardware reduce-primitive encoding baked into the SDMA descriptor (3 documented ops). SDMA_CCETYPE is the host runtime's superset carrier that also names FMA (the scale-operand reduce), EXT and GCE (extended/generic CCE forms). They share the {0,2,3} encoding, so the host value drops straight into the HW descriptor. The byte-level proof of the subset relationship is the kbin_cce_op_to_sdma_cce_op remap (CSWTCH.21 = {1, 0, 3, 2} @0x9d6e00), which renumbers a kbin op into the SDMA op space. [HIGH/OBSERVED.]

5.3 The dtype pass-through chain

The element dtype passes through with no re-encoding across ISA → SDMA → public:

NOTE — the 0xB/11 aliasing. SDMA_DTYPE carries both SDMA_DTYPE_FP32R=11 and SDMA_DTYPE_RESERVED=11 (two const_value 11 enumerators), surfacing the FP32 RTL note "0xB reserved for FP22 partial fp32". nrt_dtype likewise aliases UNKNOWN=0 with INVALID=0. [HIGH/OBSERVED.]

5.4 cce_dtypes — the reducible-dtype seed table (.rodata @0x9b9f40)

The dtypes the SDMA CCE reduce path seeds descriptors for. 6 entries of {u64 dtype, u64 group}, dumped byte-exact:

Plain FP32 (0x0A) and the integer dtypes are absent — the CCE all-reduce is a {BF16, FP16, FP32R, FP8} float reduce. [table HIGH/OBSERVED; "exhaustive reducible set" MED — it is the descriptor-seed set.]

6. The WAIT/UPDATE sync-mode families

Every TPB instruction (including the barriers and collectives) can hold an inline EVENTS block with one wait and one update primitive. The two enums split into an EVENT family (1-bit flag) and a SEMAPHORE family (32-bit counter). SYNC_BARRIER (0xD5) uses the EVENT family; CORE_BARRIER (0xD8) uses the SEMAPHORE family. The encoding regularity: +0x10 = COMPLETE variant (fires after the instruction fully completes, vs READ = after reads-done), +0x80 = REG-operand variant.

6.1 cayman / mariana / sunda (NC-v3/v4/v2) — the common form

WAIT_MODE (common.h:313, 1 B):

UPDATE_MODE (common.h:347, 1 B) — the arrive side:

[HIGH/OBSERVED @common.h:313-330 / 347-370.]

6.2 maverick (NC-v5) — DIVERGES

CORRECTION / GENERATIONAL DELTA. On NC-v5 (maverick), WAIT_MODE and UPDATE_MODE are a different enum from the other three gens. The barrier op pages diffed the barrier structs (byte-identical across all four arches) but not the mode enums, so this delta was not previously flagged. Confirmed this pass by a 4-arch md5 diff: cayman == mariana == sunda; maverick differs.

WAIT_MODE (maverick, common.h:331):

• DROPS the entire EVENT family — WAIT_FOR_EVT_{SET, SET_THEN_CLEAR, CLEAR, CLEAR_THEN_SET} (0x6/0x7/0xE/0xF) are gone.
• KEEPS SEM_*_IMM (0x1..0x5) and SEM_*_REG (0x81..0x85).
• ADDS WAIT_FOR_SEM_{EQ,LT,LE,GT,GE}_REG_OFFSET = 0x91..0x95 (register-offset operand wait form).
• ADDS UNORDERED = 0xFE (verbatim: "the instruction will not wait on any wait condition … faster than 'None' as it avoids hardware synchronization through the semaphore block").
• INVALID = 0xFF kept.

UPDATE_MODE (maverick, common.h:367): DROPS the EVENT family (EVT_SET/CLR_READ 0x1/0x2, EVT_*_COMPLETE 0x11/0x12) — only the SEMAPHORE INC/DEC/ADD/SUB/WR (READ + COMPLETE) forms remain.

Plus a new maverick-only enum NEURON_ISA_TPB_EVT_SEM_NONBLOCKING_CMD (common.h:388): NOP=0x40 SEM_INC=0x43 SEM_DEC=0x44 SEM_ADD=0x45 SEM_SUB=0x47 SEM_WRITE=0x49 READ_SEMAPHORE=0x60 READ_EVENT=0x61 — a separate non-blocking event/semaphore command space.

Re-implementation impact. A SYNC_BARRIER (event-based on v2/v3/v4) cannot be lowered the same way on v5: WAIT_FOR_EVT_SET does not exist there, so the runtime must express the same handshake through the SEMAPHORE forms or EVT_SEM_NONBLOCKING_CMD. [enum divergence HIGH/OBSERVED; the "v5 folded events into the semaphore/nonblocking space" reading is INFERRED MED.]

7. The cc_op firmware command word

The NCFW spad-control collective-op entry is the firmware's per-step program word: {1-byte header @+0} + {cc_op command word @+1}. NRT asserts spad_ctrl->header.cc_op == 1 (header bit0 = "this entry is an active collective op"). The command-word layout (see the NCFW config schema ring-protocol-config-command and spad-ccop-tsync):

// cc_op command word (entry + 1)
struct cc_op {
    // byte 0
    uint8_t algo_type     : 4;  // = low nibble of enc_alg_type (§3.3): RING0..BW_OPT_MESH10
    uint8_t algo_sub_type : 3;  // = enc_alg_mesh_type (§3.4): FULL0/GROUPED1/TRN2_2/SWITCH3
    uint8_t trigger_next  : 1;  // ring/chain step flag (ties to INSTR_CHAINING, §2.4)
    // byte 1
    uint8_t reporter            : 1;  // this channel is the leader/reporter
    uint8_t ring_wait_complete  : 1;
    uint8_t ring_send_complete  : 1;
    // +0x3 union, selected by algo_type:
    union {
        uint32_t channel_list;       // RING family: bitmask of the 32 ring channels
        struct {                     // MESH family:
            uint16_t sema_shift_offset;  // +0x3
            uint16_t sema_mask;          // +0x5  (indexes the enc_mesh_event_type window, §3.6)
        };
    };
};

The single algo_type switch binds a spad entry to an algorithm: RING/KANGARING/SINGLE_CYCLE_RING → NCFW ring channel tape; MESH/*_MESH → NCFW mesh event tape (with the sema_shift_offset/sema_mask overlay); HIER/*_RDH → NCFW hierarchical intra+inter legs.

NOTE — the reduce op is NOT in the cc_op word. The NCFW disasm reads no SDMA_CCETYPE-width field in the command word. The reduce arithmetic rides the SDMA CCE descriptor (SDMA_CCETYPE, §5.1) plus the host cc_op_info{op_type}. So spad.algo_type = "how to move/route"; SDMA_CCETYPE = "what to compute". [OBSERVED-absence HIGH; the algo_type≡enc_alg_typenibble identity is MED — width(4b) + shared vocabulary +cc_op_info{alg} carrier; the host→device write crosses into the Xtensa-LX NCFW core, for which no disassembler ships.]

8. The (op × scope × alg) legality table

The host __select_algorithms assigns an enc_alg_type per LEG; each leg's legal set is one of the .rodata assertion strings below (dumped byte-exact this pass). A hierarchical collective carries FIVE per-leg choices — the runtime log string (@0x7ed4b0, OBSERVED) is: "Hier algorithm selections - alg_intra_allg %d alg_intra_redsct %d alg_inter_allr %d alg_inter_allg %d alg_inter_redsct %d".

As a matrix (✓ = legal):

The membership logic, as the runtime expresses it (each row is a literal C assertion, reproduced naming the real symbol):

// per-leg legality asserts (the .rodata strings above; __select_algorithms output)
assert(alg_intra_allg   == ENC_ALG_RING || alg_intra_allg   == ENC_ALG_KANGARING);
assert(alg_intra_redsct == ENC_ALG_RING || alg_intra_redsct == ENC_ALG_KANGARING);
assert(alg_inter_allg   == ENC_ALG_RING || alg_inter_allg   == ENC_ALG_INTER_RDH
       || (alg_inter_allg == ENC_ALG_MESH) || inter_metaring);
assert(alg_inter_allr   == ENC_ALG_RING || alg_inter_allr   == ENC_ALG_INTER_RDH
       || alg_inter_allr == ENC_ALG_SINGLE_CYCLE_RING
       || (alg_inter_allr == ENC_ALG_MESH) || inter_metaring);
assert(alg_inter_redsct == ENC_ALG_RING || alg_inter_redsct == ENC_ALG_INTER_RDH
       || (alg_inter_redsct == ENC_ALG_MESH) || inter_metaring);

Key gating facts (OBSERVED):

• SINGLE_CYCLE_RING is all-reduce-only. enc_can_post_single_cycle_ring (@0xfaa80) guards op_type == 1 (ENC_ALLREDUCE): the 4th arg (enc_op_type → ebp) is tested cmp $0x1,%ebp ; jne reject (@0xfaadd). It appears in the inter all-reduce row only. Strings "Single Cycle ALLR", "NEURON_RT_DBG_SINGLE_CYCLE_RING_ALLR_CC" confirm.
• KANGARING is intra-only (intra all-gather + intra reduce-scatter); never inter.
• MESH (and inter_metaring) is an inter alternative for all three reducing legs.
• A hierarchical all-reduce decomposes as intra reduce-scatter → inter all-reduce → intra all-gather, so it composes the rows above.
• SB2SB op gating: "We do not support SB2SB for op type %d" — only a subset of op types use the on-chip SB2SB (0xBF) leg.

[legality strings HIGH/OBSERVED — re-dumped this pass; the matrix is the direct transcription. Which numeric alg a given (world-size, dtype, topology) resolves to depends on the enc_can_post_* thresholds — MED, not enumerated.]

9. Ring / mesh sub-selectors (summary)

• enc_alg_mesh_type (firmware algo_sub_type, §3.4): FULL0/GROUPED1/TRN2_2/SWITCH3/INVALID4. Picked by algo_sub_type bits[4:6] of the cc_op word (§7).
• reduction_type_t (ring/kangaring read/write fold pattern, §3.5): RING_2R1W0/RING_2R2W1/KANGARING_NR1W2.
• enc_mesh_event_type (mesh event-tape kinds, §3.6): the 61-event tape, phase-partitioned COMMON/MESH/A2A/RDH.
• encd_neigh (SB2SB peer selector, §3.7): LOCAL0/NEXT1/PREV2/GATEWAY3/PEER_RMTV4/PEER_RMTV2_5/PEER_LOCAL6/NEXT_PEER_RMTV7/INVALID8.

10. Cross-arch stability

4-arch md5 diff this pass (sunda v2 / cayman v3 / mariana v4 / maverick v5):

The host enc_*/SDMA_*/nrt_* enums live in a single libnrt.so that serves all gens (one binary, no per-arch divergence). CAYMAN = NC-v3. See the master capability matrix for the full cross-gen support view.

VERIFICATION NOTE. v2–v4 enum bodies are byte-grounded across all four shipped header copies. The maverick (v5) header is present and its WAIT_MODE/UPDATE_MODE/EVT_SEM_NONBLOCKING_CMD divergence is OBSERVED; where a v5-only interior is not separately corroborated by the binary it is flagged INFERRED inline.

Cross-references

• Generic collective + the in-DMA reduce mapping: TriggerCollective (0xC8)
• v2 SBUF-tensor collective + the _ext enums: TriggerCollective2 + Ext (0xD9/0xDA)
• All-reduce + reduction_type_t ring pattern: PSEUDO_TRIGGER_ALL_REDUCE (0xC7)
• The real HW SB2SB iDMA leg + LNC_SIZE_FMT: SB2SB / S3D3 Collective (0xBF)
• The CCE_OP ⊂ SDMA_CCETYPE byte remap (CSWTCH.21): CCE-in-transfer reduce
• P2P send/recv (peer_id/is_send, ENC_SEND=5/ENC_RECV=6): SENDRECV (0xCB)
• Per-iteration rank-id / GID inject: Rank-ID / GID-Load (0xDB/0xDC)
• RDMA gather variants: RDMA gather pseudo-ops
• Barriers (the WAIT/UPDATE families in context): Sync Barrier (0xD5), Core Barrier (0xD8), DMA Barrier (0xC3)
• The firmware cc_op command-word schema: Ring-protocol config command, SPAD cc_op / tsync
• Cross-generation support: Master capability matrix