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Environment Variable Catalog (NEURON_RT_*)

All addresses, offsets, defaults, and env-var spellings on this page apply to libnrt.so from aws-neuronx-runtime-lib 2.31.24.0-0b044f4ce (real file libnrt.so.2.31.24.0, SONAME libnrt.so.1, build-id 8bb57aba0fb2e0035f1d88e9fc4fb3e7387c102e, git 0b044f4ce). The ELF is not stripped and carries full DWARF v4 + a 24,864-entry .symtab; every variable name is read verbatim from NUL-terminated .rodata tokens and every destination field is the DWARF struct member the parse callsite stores into. All PT_LOAD segments are identity-mapped (.text/.rodata/.bss VMA == file offset). All addresses are analysis VMAs. Other versions will differ.

Part IV — Userspace Runtime Core / REFERENCE catalogue · Evidence grade: Confirmed (getenv→field map) — names are verbatim .rodata; destination fields are the lea OFF(%base),%rdx argument joined to the DWARF layout of the two config structs; defaults are the inline 2nd-argument immediate of the typed nrt_config_parse helper where recovered. Rows whose setter is outside nrt_config_parse_init_config are confidence-tagged. · back to index

Abstract

This page is the exhaustive control surface of the Neuron Runtime: every NEURON_RT_* and genuine NEURON_* environment variable the runtime recognizes, anchored to the getenv callsite that reads it and the config-struct field it writes. The runtime ingests its entire environment once, at nrt_init time, inside one master parser — nrt_config_parse_init_config @0x8a1d0 — and freezes the result for process lifetime. The familiar reference frame is a classic parse-once config block (the shape of an OpenMP OMP_* scan or a CUDA CUDA_* ingest), with one structural wrinkle a reimplementer must reproduce: the destination is two distinct structs, and only the base register of the destination lea distinguishes them. The config-structs page owns the field-by-field layout of both aggregates; this page owns the name → callsite → field direction of the same mapping.

The whole 123 MB object imports exactly three libc env primitives: getenv@GLIBC_2.2.5 (PLT 0x3cfd0, 43 call sites), secure_getenv@GLIBC_2.17 (PLT 0x3d9d0, 4 sites — all in vendored std::filesystem::temp_directory_path, not Neuron), and a Rust std::sys::env::unix::getenv closure (1 site, in the neuron_rustime bridge). Almost no NEURON_RT_* var is read at a bare getenv site; instead the master parser builds the variable name as a std::string from a .rodata literal, supplies the default as the helper's 2nd argument, and passes &dest (the 3rd argument, %rdx) pointing into one of the two structs — a typed nrt_config_parse(name, default, &dest) helper then does getenv(name), falls back to the default on miss, and parses into *dest. The destination is either the 656 B static singleton nrt_config (nrt_config_t @.bss 0xc5c480, written nrt_config_0.<field>) or the 296 B heap nrt_global_config (nrt_global_config_t, *ngc @.bss 0xc5c460, read everywhere through nrt_gconf() @0x82670).

A NUL-split .rodata token sweep, cross-checked against the standalone string table, enumerates 138 distinct NEURON_RT_* tokens (134 unique vars + the 4 LOG_LEVEL/LOG_LEVEL_/LOG_LOCATION/LOG_LOCATION_ plain/per-component forms) and 9 genuine non-RT NEURON_* vars. The remaining ~1,540 NEURON_* tokens are enum-value constants (NEURON_ISA_*, NEURON_MEMALLOC_*, NEURON_DM_*, NEURON_DRIVER_FEATURE_*, NEURON_POD_*), not env vars, and are excluded. This is a reference catalogue, so it takes the deliberate style-guide exception to the 40-row table rule: the catalogue table below is the body of the page, every row carrying name, type, default, destination field (struct + DWARF offset), effect, and a confidence tag.

Reimplementation Contract

  • One parser, one pass, two structs. All init-time ingestion is nrt_config_parse_init_config @0x8a1d0. It calloc(0x128, 1)s the gconf, fills both structs field-by-field from the environment, then publishes the gconf via ngc = <ptr>. Reproduce the base-register discriminator: a lea OFF(%rax),%rdx where %rax = nrt_config @0xc5c480 writes the 656 B static struct (notated cfg.X below); a lea OFF(%rcx|%r14),%rdx where the base is the calloc'd gconf writes the 296 B heap struct (notated gcfg.X). Same offset, different struct — do not merge them.
  • The default is the helper's 2nd argument. For every typed parse, the parse-time default is the literal immediate in %esi/%rsi at the call. Where that column reads , the default is sourced from a struct constant, a prior value, or an arch-dependent branch (called out per-row), not an inline immediate.
  • A handful of vars bypass the typed family. LOG_LEVEL/LOG_LOCATION (and their _-suffix per-component forms), FAKE_INSTANCE_TYPE, VIRTUAL_CORE_SIZE, the two [NEW] vars, and the six FP8_* vars at load time use direct getenv in their own functions; these rows name that function instead of an init line.
  • Some recognized vars are not parsed in init_config. The [MED]-tagged rows (NINFER, EXEC_TIMEOUT, the *_BOUND_CHECK pair, INST_VALIDITY_CHECK, ONE_TMPBUF_ENABLE, IO_RING_CACHE_SIZE, …) are recognized names whose getenv lives in the execute/translate/load path (other cells' scope); their subsystem is known but the exact callsite/default is not owned here. A reimplementer must wire them, but their precise predicates belong to the load/exec pages.
Master parsernrt_config_parse_init_config @0x8a1d0 (23,088 B) — builds name strings, fills both structs
getenv PLTgetenv@GLIBC_2.2.5 @0x3cfd0 (43 Neuron call sites)
secure_getenv PLT@0x3d9d0 (4 sites — vendored std::filesystem, not Neuron)
Static struct (cfg)nrt_config @.bss 0xc5c480nrt_config_t, 656 B, read nrt_config_0.<field>
Heap struct (gcfg)nrt_global_config_t, 296 B, *ngc @.bss 0xc5c460, read nrt_gconf()->field
gconf accessornrt_gconf @0x82670 (return ngc;)
Recognized tokens138 NEURON_RT_* (134 unique + 4 log forms) + 9 genuine NEURON_*
Excluded~1,540 NEURON_* enum-value constants (NEURON_ISA_* etc.) — not env vars

CORRECTION (NX-023 — single-struct model) — an earlier scan recorded a single config object and placed the FP8 fields "in the config struct" at +252..+260. In truth those FP8 fields live in nrt_global_config (gcfg), and nrt_config_t+252 is fail_on_nan — the two structs were conflated. nrt_gconf() @0x82670 returns the 296 B ngc, not the 656 B static singleton; 117 consumer sites read nrt_gconf()->field. Confirmed by the DGE consumer translate_one_pseudo_dge_instr_v2 @0x322c40 (call nrt_gconf; and 0x1c(%rax) = gcfg.dbg_disable_dge+28; cmpb $0,0x24(%rax) = gcfg.dbg_vector_dge_skip_notif+36). See config-structs for the full two-struct reconciliation.


At a Glance — the Ingestion Shape

Before the catalogue, the three ingestion mechanisms a reimplementer must reproduce. Every catalogue row uses one of these.

MechanismHow the value is readVars using it
Typed parse familynrt_config_parse(name, default, &dest)getenv inside the helper; default = 2nd arg; &dest = %rdx into cfg/gcfg~99 vars in init_config (the bulk)
Direct getenvA named orchestrator calls getenv(name) itself and parses with its own grammarLOG_LEVEL/LOCATION (+_ forms), FAKE_INSTANCE_TYPE, VIRTUAL_CORE_SIZE, FP8 re-read, COMPRESS_RG [NEW], PROCESS_TAG [NEW]
Out-of-init_configgetenv in the execute / translate / NEFF-load path; recognized name, setter not owned here[MED]-tagged rows

The typed family (all take a std::string name, getenv inside):

HelperAddressParses to
nrt_config_parse(string, long, long&)0x7ff20signed int
nrt_config_parse(string, uint, uint&)0x81120unsigned int (most common)
nrt_config_parse(string, ulong, ulong&)0x813d0unsigned long
nrt_config_parse(string, bool, bool&)0x81a90bool/flag (most common)
nrt_config_parse(string, char*, char*&)0x80720C-string/path (strdup'd)
nrt_config_parse_number_range<uint,true>(string, vector&)0x91040uint range/list
nrt_config_parse_numerical_error_verbosity0x81cb0verbosity enum
parse_hbm_scrub_init_val0x815e0hbm_scrub_init_val + scrub_hbm
parse_cc_alg_types0x89680cc_allowed_alg_types bitmap
parse_vnc_config0x83b40virtual_core_size (direct getenv)
parse_visible_virtual_cores0x85170visible_virtual_cores vector
parse_low_latency_tasks_cpu_affinity0x85c70cpu_set_t mask
get_enc_proxy_histogram_config0x847f0cc_proxy_histogram_config sub-struct

The Catalogue

Reference-catalogue table (style-guide exception to the 40-row limit). Notation: cfg.X = nrt_config_t field at nrt_config @0xc5c480 (656 B static); gcfg.X = nrt_global_config_t field at *ngc (296 B heap, via nrt_gconf()). The Config Field column gives the field name and its DWARF offset, consistent with config-structs. Default is the inline 2nd-argument immediate where recovered; ⇒ sourced from a struct constant / prior value / arch branch. Effect notes the consumer behavior; the parse callsite address is the getenv-bearing helper invocation. Rows are grouped by subsystem.

A — Core Visibility / Topology / Instance

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_NUM_CORESuint0cfg.num_cores +12Requested logical-core count (0 ⇒ whole device); parse @0x8a74cHIGH
NEURON_RT_VISIBLE_CORESrange/listcfg.visible_virtual_cores +16Visible-LNC list; parse_visible_virtual_cores @0x8a845HIGH
NEURON_RT_VIRTUAL_CORE_SIZEuintcfg.virtual_core_size +8LNC fusion size; parse_vnc_config direct getenv @0x83ce7HIGH
NEURON_LOGICAL_NC_CONFIGstring2cfg.virtual_core_size +8Logical-NC topology; parse_vnc_config @0x8a683HIGH
NEURON_RT_NINFERuint(vnc inflight)Per-vNC inflight count; nrt_get_visible_vnc_count, not in init_configMED
NEURON_RT_RESET_CORESbool1cfg.reset_cores +64Reset cores on init; parse @0x8acbdHIGH
NEURON_RT_FAKE_INSTANCE_TYPEstringcfg.fake_family +340 / cfg.fake_size +344 / cfg.funtime +337Simulation/"funtime" mode; nrt_config_parse_funtime @0x8379f, mirrored to gcfg.funtime +184HIGH
NEURON_RT_ULTRASERVER_MODEenum0gcfg.ultraserver_mode +40UltraServer topology mode; parse @0x8d634HIGH
NEURON_RT_ULTRASERVER_SINGLE_NODEboolgcfg.ultraserver_mode +40Forces ultraserver_mode=4; direct getenv in init pathMED
NEURON_DEVICE_COUNTuint(device-count override)Device-count override; init-path direct getenvMED
NEURON_SIM_DEBUG_FLAGSuint'U' (0x55)cfg.sim_debug_flags +48Simulator debug bitfield; parse @0x8abeaLOW

B — DGE / Instruction-Validity / Bounds (Security-Relevant)

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_DBG_DISABLE_DGEuint0gcfg.dbg_disable_dge +28Per-engine bitmask; 0xFF disables DMA Generation Engine on all TPB engines → software-descriptor path; parse @0x8d397HIGH
NEURON_RT_DBG_DISABLE_DGE_BOUND_CHECKuint0gcfg.dge_disable_bound_check +32Removes index/address bounds check around gather/scatter DGE descriptors — a NEFF out-of-range index can drive an OOB device DMA; parse @0x8d47dHIGH
NEURON_RT_DBG_VECTOR_DGE_SKIP_NOTIFbool0gcfg.dbg_vector_dge_skip_notif +36Skip vector-DGE completion notif; parse @0x8d55cMED
NEURON_RT_ENABLE_DGE_NOTIFICATIONSbool(model param)Enable DGE notifications; model-param path, not init_configMED
NEURON_RT_DBG_INST_VALIDITY_CHECKboolenabled(sequencer param)Per-instruction validity check; translate pathMED
NEURON_RT_DBG_INDIRECT_MEMCPY_BOUND_CHECKbool(translate param)Indirect-memcpy range gate; translate pathMED
NEURON_RT_DBG_EMBEDDING_UPDATE_BOUND_CHECKbool(translate param)Embedding-update range gate; translate pathMED
NEURON_RT_DBG_SB_MEMSETbool(state-buffer debug)State-buffer memset debug; execute pathMED

C — DMA / Descriptor / Prefetch

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_DBG_DMA_PACKETIZATION_SIZEuint0x1000 (cap 0xFFFFF)cfg.dma_packetization_size +212DMA packet size, range-checked; parse @0x8dfbaHIGH
NEURON_RT_DBG_DMA_PRIO_PKT_SIZEuint[5]gcfg.dma_prio_pkt_size +44Per-priority DMA packet sizes; number-range parse in init_configMED
NEURON_RT_DISABLE_PACK_DESCRIPTORSbool0cfg.v2_disable_pack_descs +208Disable descriptor packing; parse @0x8e044LOW
NEURON_RT_DBG_M2S_PREFETCH_THRESHOLDuint0cfg.m2s_prefetch_threshold +328Mem→stream prefetch threshold; parse @0x8e48fLOW
NEURON_RT_DBG_S2M_PREFETCH_THRESHOLDuint0x77 (119)cfg.s2m_prefetch_threshold +332Stream→mem prefetch threshold; parse @0x8e4ebLOW
NEURON_RT_DBG_DIRECT_BAR4_WRITE_SIZEuint0x1000 if arch>2, else 0gcfg.direct_bar4_write_size +208Direct BAR4 write size; parse @0x8ec29MED
NEURON_RT_INSTR_FETCH_ON_H2Dbitmap/bool= (arch>2)gcfg.instr_fetch_h2d_bitmap +228Instruction-fetch-on-H2D; number-range + bool, parse @0x8da92 / @0x8e20cMED
NEURON_RT_ENABLE_DMA_TRACINGbool(DMA tracing flag)DMA tracing; init/inspect pathMED
NEURON_RT_DBG_DISABLE_RMV_DST_ROUTINGboolgcfg.dbg_disable_rmv_dst_routing +195Disable RMV dst routing; parse @0x8c8f1; legacy alias …_RMV_DST_ROUTE also presentMED
NEURON_RT_IO_RING_CACHE_SIZEuint(io_ring_cache_size)I/O ring cache size; execute/load pathMED
NEURON_RT_ERROR_NQ_COALESCEbool0cfg.notif_error_nq_coalesce +94Coalesce error-NQ entries; parse @0x8cfddLOW
NEURON_RT_DBG_ZEROCOPYbool0gcfg.test_zerocopy +204Zero-copy test path; parse @0x8b03bLOW

D — Collectives (CC / RDH / Mesh / Proxy)

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_CC_ALG_TYPESbitmapcfg.cc_allowed_alg_types +200CC algorithm-type bitmap; parse_cc_alg_types @0x8c4adHIGH
NEURON_RT_CC_CHANNEL_BUFFER_Nuint8cfg.cc_nr_channel_chunks +192CC channel-buffer chunk count; parse @0x8c368MED
NEURON_RT_CC_CHUNK_SIZEuint0x200000 (2 MB)cfg.cc_chunk_size +196CC chunk size; parse @0x8c3e3MED
NEURON_RT_DBG_CC_CHECK_SIGSbool1cfg.dbg_cc_check_sigs +92CC signature checks; parse @0x8b665MED
NEURON_RT_DBG_CC_DMA_PACKET_SIZEint-listcfg.dbg_cc_dma_packet_size +168Per-stream CC DMA packet sizes; parse @0x8c2ed; clamped to 16 in nrt_initMED
NEURON_RT_DBG_CC_DMA_COPY_DMA_PRIO_PKT_SIZEuint[5]gcfg.cc_dma_copy_prio_pkt_size +64CC-copy DMA priority sizes (overrides PACKET_SIZE); init_configMED
NEURON_RT_DBG_CC_CCE_REDUCE_DMA_PRIO_PKT_SIZEuint[5]gcfg.cc_cce_reduce_prio_pkt_size +84CC-reduce DMA priority sizes; init_configMED
NEURON_RT_DBG_CC_FORCE_SINGLE_RANK_RGbool0cfg.dbg_cc_force_single_rank_rg +91Force single-rank replica group (WARN, UB); parse @0x8b5edHIGH
NEURON_RT_DBG_CC_INTER_MESH_MAX_NODESuint0x10 (16)cfg.dbg_cc_inter_mesh_max_node_n +164Inter-mesh max nodes; parse @0x8c25aLOW
NEURON_RT_DBG_CC_NOPbool0cfg.dbg_cc_nop +90Collectives → NOP (WARN, UB); parse @0x8b578HIGH
NEURON_RT_DBG_CC_PROXY_HISTOGRAM_CONFIGstructcfg.cc_proxy_histogram_config +480Proxy histogram profiling (5-token grammar); get_enc_proxy_histogram_config @0x8e5e6MED
NEURON_RT_DBG_CC_SORT_RGbool0cfg.dbg_cc_sort_rg +650Sort replica groups; parse @0x8ef46LOW
NEURON_RT_DBG_CC_STREAM_MODEuint1cfg.dbg_cc_stream_mode +136CC stream mode; parse @0x8b92fMED
NEURON_RT_DBG_HIERARCHICAL_CCuint0cfg.dbg_hierarchical_cc_mode +104Hierarchical CC mode; parse @0x8b7c7MED
NEURON_RT_DBG_HIER_CC_PIPELINEuint0cfg.dbg_hier_cc_pipeline +160Hierarchical CC pipelining; parse @0x8c1dfLOW
NEURON_RT_DBG_HYBRID_RING_CC_ENbool1cfg.dbg_hybrid_ring_cc_enabled +649Hybrid-ring CC enable; parse @0x8ea07LOW
NEURON_RT_DBG_KANGARING_CCuint0cfg.dbg_kangaring_cc_mode +108Kangaring CC mode; parse @0x8b83cMED
NEURON_RT_DBG_MESH_CCbool1cfg.dbg_mesh_cc_mode +140Mesh CC mode; parse @0x8bd23MED
NEURON_RT_DBG_MESH_CHANNEL_BUFFER_SIZEulong0x800000 (8 MB)gcfg.dbg_mesh_ch_buf_size +264Mesh channel buffer; parse @0x8b9adMED
NEURON_RT_DBG_MESH_DOUBLE_BUFbool1cfg.dbg_mesh_double_buffer +141Mesh double-buffering; parse @0x8bd9eLOW
NEURON_RT_DBG_RDH_CCuint1cfg.dbg_rdh_cc_mode +116RDH CC mode; parse @0x8b8b4MED
NEURON_RT_DBG_RDH_DOUBLE_BUFbool0cfg.dbg_rdh_double_buffer +142RDH double-buffering; parse @0x8be16LOW
NEURON_RT_DBG_INTRA_RDH_CHANNEL_BUFFER_SIZEulong40 MB (80 MB arch4)gcfg.dbg_intra_rdh_ch_buf_size +272Intra-RDH channel buffer; parse @0x8ba4aMED
NEURON_RT_DBG_INTER_RDH_CHANNEL_BUFFER_SIZEulong0x2000000 (32 MB)cfg.dbg_inter_rdh_ch_buf_size +120Inter-RDH channel buffer; parse @0x8bb3dMED
NEURON_RT_DBG_INTER_RDH_RECV_WINDOW_Nuint0cfg.dbg_inter_rdh_recv_window_n +128Inter-RDH recv window; parse @0x8bbb5LOW
NEURON_RT_DBG_ENFORCE_RDH_GLOBAL_HANDSHAKEuint0gcfg.dbg_enforce_rdh_global_handshake +284RDH global handshake; parse @0x8bac5LOW
NEURON_RT_DBG_ENFORCE_MESH_GLOBAL_HANDSHAKEuint0cfg.dbg_enforce_mesh_global_handshake +144Mesh global handshake; parse @0x8be8eLOW
NEURON_RT_DBG_SINGLE_CYCLE_RING_ALLR_CCuint2cfg.dbg_single_cycle_ring_allr_mode +112Single-cycle ring all-reduce; parse @0x8bc2dMED
NEURON_RT_DBG_EARLY_COMPLETIONbool1cfg.dbg_proxy_early_completion +148Proxy early completion; parse @0x8bf09MED
NEURON_RT_DBG_EARLY_POSTINGbool1cfg.dbg_proxy_early_posting +149Proxy early posting; parse @0x8bf84MED
NEURON_RT_DBG_FORCE_2DEV_PROXYbool0cfg.dbg_force_use_2dev_proxy +648Force 2-device proxy; parse @0x8e9abLOW
NEURON_RT_RANKS_PER_NETWORK_PROXYuint1cfg.ranks_per_network_proxy +152Ranks per network proxy; >1 requires HW exec barrier; parse @0x8bfffHIGH
NEURON_RT_ROOT_COMM_IDstringNULLcfg.cc_root_comm_id +40Collective root comm id (required for collective NEFF); nrt_cc_global_comm_init, getenvstrdupHIGH
NEURON_RT_ENABLE_RG_VALIDATIONboolgcfg.enable_replica_group_validation +194Replica-group validation; parse @0x8c808MED
NEURON_EXPERIMENTAL_COMPRESS_RG [NEW]bool(replica-group compression)RG compression; enc_parse_replica_groups direct getenv @0x11ea54HIGH

E — Async Send/Recv & XU Compute (Experimental)

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_ASYNC_EXEC_MAX_INFLIGHT_REQUESTSuint0 (clamp 63)gcfg.async_exec_max_inflight_requests +24Max in-flight async reqs; clamped if >63; parse @0x8f10aHIGH
NEURON_RT_ASYNC_SENDRECV_BOOTSTRAP_PORTuintgcfg.async_sr_boot_port +104Async send/recv bootstrap port; parse @0x8cac2LOW
NEURON_RT_ASYNC_SENDRECV_EXPERIMENTAL_ENABLEDboolgcfg.async_sr_experimental_enabled +108Experimental async S/R enable; parse @0x8cba6LOW
NEURON_RT_XU_COMPUTE_MAX_QUEUED_REQUESTSulong8(XU compute queue depth)XU compute max queued reqs; parse @0x8f0adMED

F — FP8 Numerics / Stochastic Rounding

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_DBG_FP8_RANGE_EXTbool1gcfg.fp8_range_ext +252FP8 range extension; parse @0x8e6b7; re-read at load @0x4c33e5MED
NEURON_RT_DBG_OCP_FP8_SATbool1gcfg.ocp_fp8_sat +253OCP FP8 saturation; parse @0x8e7f5; re-read @0x4c3405MED
NEURON_RT_DBG_FP8_SNSbool0gcfg.fp8_sns +254FP8 SNS; parse @0x8e85c; re-read @0x4c3425LOW
NEURON_RT_DBG_FP8_SISbool0gcfg.fp8_sis +255FP8 SIS; parse @0x8e8c3; re-read @0x4c3448LOW
NEURON_RT_DBG_FP8_EMAX_E4M3uint8gcfg.fp8_emax_e4m3 +256FP8 E4M3 emax; parse @0x8e721; re-read @0x4c3462MED
NEURON_RT_DBG_FP8_EMAX_E5M2uint0xF (15)gcfg.fp8_emax_e5m2 +260FP8 E5M2 emax; parse @0x8e78b; re-read @0x4c347cMED
NEURON_RT_STOCHASTIC_ROUNDING_ENboolgcfg.stochastic_rounding_en +192Stochastic-rounding enable; parse @0x8ae75MED
NEURON_RT_STOCHASTIC_ROUNDING_SEEDuintgcfg.stochastic_rounding_seed +188SR seed; parse @0x8ad9aMED
NEURON_RT_DBG_CC_STOCHASTIC_ROUNDING_ENboolgcfg.dbg_cc_stochastic_rounding_en +193CC SR enable; parse @0x8af5eLOW
NEURON_RT_NUMERICAL_ERRORS_VERBOSITYenumgcfg.numerical_errors_verbosity +200Numerical-error verbosity; forced >=1 if fail_on_nan; nrt_config_parse_numerical_error_verbosity @0x8c72dMED
NEURON_RT_ENABLE_VERBOSE_NUMERICAL_ERRORSbool(verbose numerical errors)Verbose numerical errors; execute pathMED

NOTE — the six NEURON_RT_DBG_FP8_* vars are parsed once in init_config (defaults above) and re-read by direct getenv inside kelf_load_from_neff @0x4c0870 (sites 0x4c33e5..0x4c347c), where they override the FP8 config baked into the NEFF's def.json at load time. A reimplementer must honor both reads: the env value wins over the model file.

G — Ucode / NEFF Loading / Arch Select

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_UCODE_LIB_PATHcstrNULLcfg.neuron_ucode_path +224GPSIMD microcode dlopen path (attacker-controlled env ⇒ arbitrary .so load); strdup, parse @0x8e0a8MED
NEURON_RT_DBG_V4_PLUSuint0gcfg.v4_plus +232v4+ arch path (mariana vs mariana_plus, ext-ISA); parse @0x8e64dHIGH
NEURON_RT_DBG_HW_DECODE_BINS_DIRcstrNULLcfg.hw_decode_table_path +232HW-decode table dir; parse @0x8e109MED
NEURON_RT_DBG_HW_DECODE_TOGGLEuintarch: 4→11, 3→3, else 0cfg.hw_decode_toggle +240HW-decode enable; forced 0 if strict-order; parse @0x8e19bHIGH
NEURON_RT_ALLOW_LEGACY_NEFFuint0gcfg.allow_legacy_neff +0Allow legacy NEFF format; parse @0x8a2a6; re-read in kelf_loadHIGH
NEURON_RT_VALIDATE_HASHbool(NEFF hash validation)NEFF hash validation; kelf_load pathMED
NEURON_RT_DBG_SEQ_IRAM_BLOCK_SIZES_KBulong[5]gcfg.seq_instr_block_size +120Per-engine IRAM block sizes (KB<<10); po2/IRAM-divisor validated; parse @0x8ea60MED

H — Scratchpad / Tmpbuf / HBM / Memory

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_SCRATCHPAD_PAGE_SIZEulong— (value <<20)cfg.scratchpad_page_size +56Scratchpad page bytes; parse @0x8b313HIGH
NEURON_RT_ONE_TMPBUF_PAGE_SIZE_MBulong0x200 (512)(one-tmpbuf page bytes)One-tmpbuf page size; parse @0x8b293MED
NEURON_RT_ONE_TMPBUF_ENABLEbool(one_tmpbuf enable)One-tmpbuf enable; execute pathMED
NEURON_RT_DBG_SCRATCHPAD_ON_SINGLE_COREuint0gcfg.scratchpad_on_single_core +16Force scratchpad onto one core; parse @0x8b3a1MED
NEURON_RT_DBG_EXPERIMENTAL_CONTIGUOUS_SCRATCHPADuint0gcfg.experimental_contiguous_scratchpad +112Contiguous scratchpad alloc; parse @0x8b419LOW
NEURON_RT_HBM_INIT_VALuintcfg.hbm_scrub_init_val +272 / cfg.scrub_hbm +276HBM scrub fill value + enable; parse_hbm_scrub_init_val @0x8e436MED
NEURON_RT_MAP_HBMbool0cfg.map_hbm +336Map HBM into address space; parse @0x8e544MED
NEURON_RT_ENABLE_MEMORY_METRICSbool1cfg.enable_memory_metrics +216Memory-metrics emit; parse @0x8c581LOW
NEURON_RT_DBG_VERBOSE_DEV_MEMbool0cfg.dbg_verbose_log_dev_mem +93Verbose device-mem logging; parse @0x8b6daLOW
NEURON_RT_MIN_MEM_ERROR_INTERVALlong0xE10 (3600)cfg.v2_min_ignore_nc_memory_error_interval +96v2 mem-error suppress window (s); parse @0x8b752LOW
NEURON_RT_DEBUG_MEMLOG_MAX_SIZEulong0x100000 (1 MB)cfg.mem_log_size +72Device-memory log ring size; parse @0x8b132LOW
NEURON_RT_DBG_VIRTUAL_SERVER_SIZEuint0cfg.virtual_server_size +348Virtual-server core count; parse @0x8e59dMED

I — Execution Barriers / Ordering / Sync

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_DISABLE_EXECUTION_BARRIERbool0cfg.disable_execution_barrier +205Disable exec barrier; parse @0x8d0d1MED
NEURON_RT_ENABLE_HW_EXECUTION_BARRIERbool= switch_v1_familycfg.enable_hw_execution_barrier +206HW exec barrier (arch-default); parse @0x8d1dfMED
NEURON_RT_ENABLE_INTERNODE_EXECUTION_BARRIERbool1cfg.enable_internode_execution_barrier +207Internode exec barrier; parse @0x8d2c6MED
NEURON_RT_DBG_FORCE_STRICT_ORDERINGbool0cfg.dbg_force_strict_ordering +88Strict ordering; forces hw_decode_toggle=0; parse @0x8b48eMED
NEURON_RT_EXEC_TIMEOUT(exec timeout)Execution timeout; execute pathMED
NEURON_RT_DBG_DROP_EVENTSEM_NOTIFbool1 (stored !drop)cfg.notif_full_evsem +95Drop event-sem notif; parse @0x8ce9fLOW
NEURON_RT_DBG_TOPSP_SEMAPHORES_CLEAR_CHECKbool0cfg.dbg_topsp_semaphores_clear_check +157TopSP semaphore clear check; parse @0x8c0efLOW
NEURON_RT_DBG_TOPSP_EVSEM_NOTIF_ENABLEDbool0cfg.dbg_topsp_evsem_notif_enabled +204TopSP event-sem notif enable; parse @0x8c167LOW
NEURON_RT_DBG_TOPSP_SYSTRACE_INCLUDE_DEFAULT_ALGOboolgcfg.dbg_topsp_event_include_default_algo +197Include default algo in TopSP systrace; parse @0x8c9dcLOW
NEURON_RT_EMBEDDED_SEM_ENBbool0gcfg.embedded_sem_en +196Embedded semaphore enable; parse @0x8ee6eLOW
NEURON_RT_DBG_MS_ENABLE_SKIP_TPB_CONFIG_OPTbool1gcfg.enable_model_switch_skip_tpb_config_optimization +288Skip TPB-config opt on model switch; parse @0x8efb6MED
NEURON_RT_DBG_BRANCH_LABEL_ALIGN_THRESHulong0x10 (16)gcfg.br_label_align_thresh +160Branch-label alignment threshold; parse @0x8ee0aLOW

J — P2P / Misc HW / Threading

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_ENABLE_P2Pbool1gcfg.enable_p2p +116Peer-to-peer enable; gates nrt_get_dmabuf_fd export; parse @0x8bca8HIGH
NEURON_RT_DISABLE_BG_XPOSEbool0gcfg.disable_bg_xpose +224Disable background transpose; parse @0x8e952LOW
NEURON_RT_GPSIMD_STDOUT_QUEUE_SIZE_BYTESuint0cfg.pool_stdout_queue_size_bytes +132GPSIMD stdout pool bytes; parse @0x8cc8cLOW
NEURON_RT_ONE_THREAD_PER_COREbool0cfg.one_thread_per_core +156One worker thread per core; parse @0x8c077MED
NEURON_RT_LOW_LATENCY_TASKS_CPU_AFFINITYmaskcfg.low_latency_tasks_cpu_affinity_mask +352Low-latency thread affinity; parse_low_latency_tasks_cpu_affinity @0x8c654MED
NEURON_PROCESS_TAG [NEW]string(datastore process tag)NDS datastore process tag; tdrv_nds_save_process_info direct getenv @0x22f023HIGH

K — Logging / Tracing / Metrics

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_LOG_LEVELenum(nlog level)Global nlog level; nrt_config_log_level direct getenv @0x82140HIGH
NEURON_RT_LOG_LEVEL_enum(per-component nlog level)Per-component level (component name appended at runtime); nrt_config_apply_log_level @0x81515HIGH
NEURON_RT_LOG_LOCATIONstring(nlog sink)Global nlog sink location; nrt_config_log_level direct getenvHIGH
NEURON_RT_LOG_LOCATION_string(per-component sink)Per-component sink; nrt_config_apply_log_levelHIGH
NEURON_RT_LOG_COALESCING_ENABLEDboolgcfg.log_coalescing_enabled +212Log coalescing; read by nlog_init; parse @0x8a507MED
NEURON_RT_TRACE_NUM_ENTRIESulong0x100000 (1 M)cfg.max_trace_entries +80Trace ring entry cap; parse @0x8b218LOW
NEURON_RT_DBG_IO_CRCbool0cfg.dbg_io_crc +89CRC I/O tensors; parse @0x8b503LOW
NEURON_RT_DEBUG_STREAM_BUFFER_SIZEulong0x40000 (256 K)gcfg.ndebug_stream_evts_ring_size +216Debug-stream event ring size; po2-validated, ERROR otherwise; parse @0x8eed5MED

L — Inspect / Profiling

Parsed by nrt_config_parse_inspect_config @0x86760 (the NEURON_RT_INSPECT_* family) and the profiling orchestrators; destinations are the inspect-config aggregate, not cfg/gcfg.

VarTypeDefaultConfig FieldEffectConf
NEURON_RT_INSPECT_ENABLEboolinspect_configMaster inspect enableMED
NEURON_RT_INSPECT_ON_FAILboolinspect_configCapture-on-failMED
NEURON_RT_INSPECT_OUTPUT_DIRstringinspect_configOutput directoryMED
NEURON_RT_INSPECT_DEVICE_PROFILEboolinspect_configDevice profile captureMED
NEURON_RT_INSPECT_SYSTEM_PROFILEboolinspect_configSystem profile captureMED
NEURON_RT_INSPECT_HOST_MEMORYboolinspect_configHost-memory captureMED
NEURON_RT_INSPECT_CPU_UTILboolinspect_configCPU-util captureMED
NEURON_RT_INSPECT_EVENT_FILTER_NClistinspect_configPer-NC event filterMED
NEURON_RT_INSPECT_EVENT_FILTER_TYPElistinspect_configEvent-type filterMED
NEURON_RT_INSPECT_SYS_TRACE_MAX_EVENTS_PER_NCuintinspect_configMax sys-trace events/NCMED
NEURON_RT_PROFILING_MODEenum(profiling mode)Profiling mode; parse @0x8cd5fMED
NEURON_RT_PROFILE_BUF_uint (prefix)cfg.profile_buf_sizes +280Per-notif-type buffer size; suffix appended at runtime; nrt_config_profile_buf_size @0x828b0MED

M — Core Dumps / OOM / Failure Capture

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_RT_LOCAL_CORE_DUMP_DIRECTORYcstr"/tmp/neuron-core-dump/dt-%d-cid-%c"gcfg.local_core_dump_directory +168Local core-dump dir template; init_configMED
NEURON_RT_S3_CORE_DUMP_PREFIXcstrNULLgcfg.s3_core_dump_prefix +176S3 core-dump prefix; getenvstrdupMED
NEURON_RT_OOM_DUMP_DIRECTORYcstr"/tmp"gcfg.device_oom_dump_directory +8Device-OOM dump dir (path capped 200); first getenv in initMED
NEURON_RT_DBG_DUMP_INPUTS_ON_ERRlong0cfg.dump_inputs_on_err +256Dump inputs on error; parse @0x8e387LOW
NEURON_RT_DBG_INPUT_DUMP_DIRECTORYcstr"/tmp/neuron-input-dump"cfg.input_dump_directory +264Input-dump dir (len-capped); parse @0x8e3e9LOW

N — Genuine non-RT NEURON_*

VarTypeDefaultConfig Field (struct+offset)EffectConf
NEURON_NO_COMPILE_MODEbool0cfg.enable_no_compile_mode +244No-compile (pre-built) mode; parse @0x8e279LOW
NEURON_NO_COMPILE_MODE_TIMEOUTuint0x78 (120)cfg.no_compile_mode_timeout +248No-compile timeout (s); parse @0x8e2d5LOW
NEURON_FAIL_ON_NANbool0cfg.fail_on_nan +252Fail on NaN; forces numerical_errors_verbosity>=1; parse @0x8e32eMED

NOTE — experimental flags. Four knobs are explicitly experimental and a reimplementer should treat their semantics as unstable across runtime minor versions. NEURON_RT_ASYNC_SENDRECV_BOOTSTRAP_PORT (gcfg+104) and NEURON_RT_ASYNC_SENDRECV_EXPERIMENTAL_ENABLED (gcfg+108) gate the experimental point-to-point async send/recv transport — the EXPERIMENTAL_ENABLED flag is the master gate, and the bootstrap port is meaningless unless it is set. NEURON_RT_RANKS_PER_NETWORK_PROXY (cfg+152, default 1) carries an ordering precondition: a value >1 requires the HW execution barrier (enable_hw_execution_barrier, cfg+206) — init_config aborts the combination of ranks_per_network_proxy>1 with the HW barrier disabled. NEURON_EXPERIMENTAL_COMPRESS_RG [NEW] is read by direct getenv in enc_parse_replica_groups @0x11ea54, outside the master parser, and toggles replica-group compression in the collectives path.

GOTCHA — secure_getenv is a vendor red herring. Four secure_getenv call sites exist, all inside vendored std::filesystem::temp_directory_path; none is a Neuron knob. A reimplementer scanning for the env surface by grepping *getenv PLT references must filter these out — and likewise exclude the ~1,540 NEURON_* enum-value constants (NEURON_ISA_*, NEURON_MEMALLOC_*, NEURON_DM_*, NEURON_DRIVER_FEATURE_*, NEURON_POD_*), which look like env vars by spelling but are never passed to getenv.


Boundary Edges

A handful of recognized vars are owned by other subsystems; this page records the env→field write only, and the consumer semantics live elsewhere.

Var(s)Owning subsystem
DGE/validity/bounds consumer logic (translate_one_pseudo_dge_instr_v2/v3, sequencer_setup_instr)NEFF load / translate and ISA pseudo-lowering
INST_VALIDITY_CHECK, *_BOUND_CHECK pairmodel-build translate params (not in cfg/gcfg) → translate cells
ALLOW_LEGACY_NEFF gate + FP8 re-read (kelf_load_from_neff @0x4c0870)NEFF load pipeline
DBG_V4_PLUS ext-ISA consumptionext-ISA provider
PROCESS_TAG [NEW]Neuron DataStore (tdrv_nds_save_process_info)
COMPRESS_RG [NEW]collectives engine core (enc_parse_replica_groups)
LOG_LEVEL/LOCATION enum decode + nlog wiringLogging (nlog)

Cross-References