LLO Opcode Master Table

Every opcode value, mnemonic, slot name, and address on this page was read byte-exactly from libtpu.so in the libtpu-0.0.40-cp314 wheel (BuildID 89edbbe81c5b328a958fe628a9f2207d, not stripped). Other versions differ.

Abstract

This appendix is the single consolidated reference table for the LLO opcode space — the one table a reimplementer keeps open while building a TPU back end. LLO (Low-Level Optimizer IR) is the TPU-specific late compiler IR below MHLO/TLP and above the per-generation TensorCore bundle encoders; its in-memory opcode enum xla::jellyfish::LloOpcode is a dense, zero-based, 461-value numbering (0x000..0x1CC), and every value is named in the relocated opcode_name table at 0x21ccfef0. The authoritative per-family facts live on the isa/ deep pages; this page aggregates them into one master opcode→mnemonic→slot→semantics→per-gen table, grouped by the bundle slot (functional unit) each opcode is encoded into.

The table is organized by slot family, not by numeric run, because the value space interleaves: LloOpcodeIsVector is a dense switch, not a >= threshold test, and (for example) kVectorReadIar (1) is vector while kLog (5) is not. Each slot section below enumerates the opcodes that the per-slot encoder serializes into that slot, with the numeric LloOpcode value, a one-line semantics, and per-generation availability where it varies (the five codec lineages: jxc Jellyfish/Dragonfish v2/v3, pxc Pufferfish v4, vfc/vxc Viperfish v5p, glc Ghostlite v6e, gfc 6acc60406 TPU7x). The bit-level field encodings — where each opcode's operands land in the 41/51/64-byte bundle — are not repeated here; they live on the per-slot deep pages, which every section cross-links.

Three index spaces must not be conflated with LloOpcode, and a reimplementer who confuses them mis-decodes every program: the LloOpcodeProto wire enum (1-based, max 499, 38 reserved gaps, see LloOpcode↔Proto); the MC MCInst opcode space the LLVM-MC emitter dispatches on (LloOpcode + 499, gated <= 0x1F2); and the GhPerf::Instruction cost-grid enum. LloOpcode is the one all the others map from. A representative sample of the values in this table was re-verified against the binary classifiers and converters (see Verification); where a deep page and the binary agreed they were taken as CONFIRMED, and no disagreements were found.

For reimplementation, the contract this table supports is:

• The opcode numbering is gen-invariant — the same LloOpcode value means the same opcode on every generation; what changes per gen is the valid subset (sparsity is v5+, cmem-load is PF-only) and the bundle encoding, not the number.
• The slot a value occupies (which bundle field the per-gen encoder serializes it into) is recovered from the per-slot classifier switches and encoder dispatch, listed per section.
• The per-gen availability column flags opcodes that exist only from a given generation (F8 converts PF+, stochastic-round VF+, S4/U4 matmul PF+, BarnaCore vs SparseCore split).
• The bit encodings are deferred to the per-slot deep pages; this table is value↔mnemonic↔slot↔semantics only.

Slot Families at a Glance

Eleven functional-unit families partition the 461 opcodes (plus a 33-opcode BarnaCore/SparseCore block). The count column is the number of distinct LloOpcode values the family owns; the owning page is the deep page that documents that slot's bit encoding. Values are mostly-contiguous bands; the exact members are in the per-family sections below.

NOTE — the sparsity slot is not yet recovered. The structured-sparsity slot (Sparsity Slot (v5+)) is a v5+/Viperfish-and-later feature whose backing analysis is still open; no distinct LloOpcode values for it have been pinned. It is listed for completeness but contributes no rows to the tables below. A reimplementer targeting only v3/v4 can ignore it entirely.

QUIRK — 461, not 462. The "462" figure that floats around LLO documentation is the LloOpcodeProto wire enum (1-based, value-0 sentinel, max 499, 38 gaps). The in-memory LloOpcode this table indexes is exactly 461 dense values (0x000..0x1CC); LloOpcodeName traps on >= 0x1CD. Drive a switch off 462 and the last index reads past the metadata tables. See LloOpcode↔Proto.

Sequencer, Sync & FIFO-Transfer Slot (0x000..0x030)

The control-and-handshake layer: program boundaries, scheduling barriers, fences, cycle-counter reads, halt/yield, and the scalar/vector/sync-flag result-FIFO push/pop primitives that move values between the SPU, VPU, and the cross-FIFO staging registers. PC mutation (branch/call/halt) is lane-0-only; sync ops live in a separate ScalarMisc lane on v5+. The per-(gen × sequencer-type) control-flow roster is on Seq-Ops-Per-Gen.

NOTE — Push/Pop are property bits, not opcode ranges. opcode_info bit0 (Push) is set on the *Push members, bit1 (Pop) on the *Pop members. A scheduler models the V2S / sync FIFOs by reading these bits, not by a numeric range test. kScalarHalt/kScalarHaltOnError share GhPerf cost row 0x000.

SPU / Scalar-ALU Slot

The scalar control CPU lane — 32-entry SREG file, address arithmetic, branch/call/select, the dense arithmetic-and-shift tail, and the V↔S FIFO pops. The register-file-class byte (opcode_info high byte) is 1 (scalar/mask). Lane 0 owns the full set incl. branch/call; lane 1 is an ALU+halt mirror. Bit layout on SPU / Scalar Slot.

The SPU is the complement of the vector set (LloOpcodeIsScalar = !LloOpcodeIsVector), 63 opcodes total; EncodingToScalarRegister (0x1e871e40) bounds the SREG selector at > 0x1F (32 registers, 5-bit field) — verified byte-exact. The per-gen jump-table size is the per-gen scalar ISA size (JF 0..0x3E, PF ≤0x33, VF ≤0x4C, GL/GF ≤0x49).

VPU / Vector-ALU Slot

The per-lane vector ALU over the 8 sublane × 128 lane = 1024-element vreg. Register-file-class byte 2 (vector); the foldable/CSE bits (opcode_info bit5/bit6) are set on the pure-functional members. LloOpcodeIsVectorUnop (0x1d60c200) / LloOpcodeIsVectorBinop (0x1d60c680) split unary vs binary. Bit layout (6/7/8-bit opcode, 5/4/2-bit predicate per gen) on VPU Slot.

The VALU is the largest family; only the representative bands are shown. vmul.u32.u64 is a PF+ slot-pair wide multiply. The VectorAluYEncoding (0..31) source-B selector — vreg / VS0-2 ports / hardwired float constants / immediate slots — is documented on VPU Slot §Y-operand.

Convert / Pack / Unpack

Type conversions across three bands: f32→{s32,f8,hf16} and {s8,s4,u8,u4}↔bf16, the unpack/round/truncate block, and pack/compose. These gained the most across generations.

EUP / Transcendental Slot (0x128..0x14D)

The Extended Unary Pipeline computes nine transcendentals (tanh, pow2, reciprocal, log2, rsqrt, shifted-sigmoid, sinq, cosq, erf) as a deferred-result pipeline: a push (VALU slot 3 only on v5+) and a later pop from the VectorResult slot. Each function appears in four LLO forms — F32 issue-only, Bf16 issue-only, F32 issue+pop (AndPop), Bf16 issue+pop. Selector map and latency on EUP / Transcendental Slot.

Representative function-selector values (the 5-bit field, gfc/glc @ bit 183): F32 tanh=0x13, rsqrt=0x10, pow2=0x11, log2=0x12, sigmoid=0x14, reciprocal=0x15, sin=0x17, cos=0x18, erf=0x0e; Bf16 selectors differ (e.g. tanh=0x1b). The 18 *AndPop pseudo-ops (excluding 0x144) are split by LloLateDecomposer into bare push + deferred pop; LloOpcodeIsPseudoEupInstruction (0x1d60c880) classifies them via the 0x7FDFF mask — verified byte-exact.

NOTE — the EUP family is the cleanest Push/Pop illustration. Every issue-only EUP opcode sets opcode_info bit0 (Push); kVectorEupResult (0x14E) sets bit1 (Pop). CreateVectorEupResult (0x1d4d9820) asserts the push operand is in [0x128, 0x13A] before building the 0x14E pop — verified byte-exact.

Cross-Lane, Reduce & XLU-Result

Cross-lane permute/rotate/broadcast, whole/segmented reductions (min/max/add/argmin/argmax in F32 and Bf16), and the deferred-result pops (EUP, cross-lane, permute, CMEM, transpose, matmul). The 21 XLU opcodes are walked by ComputeXluOperations (0x126d9780) and emit {TransposeTile, RpuOperation, XluControlOperation} variants — see ResultFifo / ArchRegister.

kVectorXlaneResult/kVectorPermuteResult/kVectorTransposeResult share GhPerf cost row 0x1C7. kVectorTransposeClear (0x155) is the single opcode whose opcode_info word is 0x000E.

MXU — Matmul, Latch, Matprep, Result

The systolic-array op family: latch the stationary weights, matprep the moving operand, issue the matmul, drain via matres. Latch/matprep/matmul share the VectorExtended slot; matres uses VectorResult. The matmul band (0x8D..0xA5) is data-format special-cased before the property-word read. Field encoding (per-gen 6→7→8-bit opcode, the −20/−21/−25 inter-MXU twin) on MXU Slot; latch/matprep field maps on Matprep/IAR/Latch.

Per-gen dtype set: PF/VF/GL carry 8 formats {F32, If8, Bf16, Bf8} × float + {U8, S8, U4, S4} × int; gfc (v6e) is float-only 4-format {F32, E4m3, Bf16, E5m2}. MXUs per TensorCore: 1 (JF) / 4 (PF, VF) / 2 (GL, gfc). MSR banks: 1 (JF/PF) / 2 (VF/GL/gfc).

GOTCHA — the matmul push bit is data-format-dependent, not static. LloInstructionPushesToResultFifo tests the matmul band (0x8D..0xA5) via a bitmask and routes to a matmul_data_format vtable call; reading the static Push bit from opcode_info[op] for a matmul opcode gives the wrong FIFO behavior. The push depends on the data format decided at the instruction instance.

Memory Load / Store / IAR / RNG

Per-lane index-address-register (IAR) setup, the per-lane PRNG, and the load/store slots. The tier (VMEM/SMEM/CMEM/SPMEM) is selected by which slot the op occupies, not a tier bit. CMEM-load is a dedicated PF-only slot. Bit layout on Memory-Load, Memory-Store, CMEM-Load (PF).

The store window classified by LloOpcodeIsVectorStore (0x14024920) is internal {63,64,65,68,69,70} ∪ {460} — verified byte-exact ((op-63)<=7 && _bittest(0xE7, op-63) || op==460). The load window LloOpcodeIsVectorLoad (0x14024900) is {48..51} ∪ {457,458} — verified byte-exact. IarsPerTensorCore = 2 on every gen.

The Ghostlite perf classifier (GetGhostliteInstruction @ 0x1c8b1740) keys the indexed-memory ops on an IAR-present sentinel; the seven IAR-class opcodes are byte-exact (used as the IAR op-id ground truth):

QUIRK — the LLO IAR opcode number and the bundle-slot IAR opcode do not line up. LLO kVectorSetIarRaw (0x03) maps to ISA slot-opcode 4, and LLO kVectorSetIarSublane (0x04) maps to slot-opcode 3 — the Sublane/Raw encodings cross. A reimplementation that assumes LLO-opcode == slot-opcode swaps them. See Matprep/IAR/Latch §IAR.

DMA (0x0B3..0x0DA)

The 40 contiguous DMA opcodes — the largest single contiguous block — enumerate direction (HBM/VMEM/SMEM/CMEM/HIB/IMEM/Host + IOVA host) × source/destination-register variants + a WithHibUpdate family + two terminators. DMA is issued from the sequencer/scalar lane via descriptors; none set a result-FIFO Push/Pop bit (opcode_info low byte 0x00).

NOTE — the cost model prices DMA by direction-class. The 14 HBM/Host-DMA opcodes collapse to GhPerf row 0x40 and the 14 VMEM/SMEM-DMA opcodes to row 0x43; the 40 distinct LloOpcode values all exist but the latency model treats each direction family as one.

Predicate / Mask Slot

Scalar predicate (1-bit Preg, P0..P14/15) and per-lane vector mask (Vmreg, M0..M31) ops — two physically distinct register files. Compare ops produce a mask; select consumes one. There is no native predicate-AND (synthesized via De Morgan). Bit layout on Predicate Slot; the M-register rectangle on vcreate_mask.

The four Move-exclusion opcodes — kScalarMove (0x17B), kVectorMove (0x181), kVectorMaskMove (0x199), kPredicateMove (0xE6) — are skipped by the CSE/remat/fold passes. Native vcreate_mask exists only on VF/GL (synthesized via iota-compare on JF/DF/PF).

Constants, Pseudo & Call

Constants, Phi/pseudo SSA nodes, and the call/tuple group. Constants set the remat bit (opcode_info 0x50); Phi nodes short-circuit to cost 0. Address materialization is remat-able. Literals route through immediate slots — see Immediate Slot.

BarnaCore (SparseCore) Block (0x1AC..0x1CC)

The 33 highest opcodes are the BarnaCore (SparseCore) instruction set — embedding scatter/gather, sparse reduce, remote scalar writes, and the BarnaCore-local vector load/store/move. These are the opcodes the LLVM-MC emitter actually encodes (its populated InstBits_BarnaCorePxcHwMode table covers this range), unlike the TensorCore opcodes which it returns all-zero. The SparseCore scalar/vector opcode enums (the per-engine SCS/TAC/TEC scalar-ALU and vector-ALU rosters) are separate engine-family enums with their own deep pages — see SPU / Scalar Slot §SparseCore and VPU Slot.

QUIRK — the BarnaCore vector load/store opcodes (457..460) test as vector; the scalar/sync ones (428..456) test as non-vector. This is the only place the BarnaCore block straddles the vector/scalar partition, and it matters for register-class selection. The TpuSequencerType enum that selects the SparseCore engine codec is kTensorCoreSequencer(0)..kSparseCoreTileExecuteSequencer(5); TpuSequencerTypeFromProto (0x20b36300) maps proto 1..6 → internal 0..5 — verified byte-exact. BarnaCore is a pre-v5 construct (JF address-handler, PF sequencer); from v5 onward SparseCore (SCS/TAC/TEC) replaces it, and 6acc60406 (v7x) drops the TAC engine.

Per-Generation Availability Summary

LloOpcode numbering is gen-invariant; the valid subset grows per silicon. The codename → namespace map: jxc = Jellyfish (jellyfish::isa) + Dragonfish (alias); pxc = Pufferfish; vxc/vfc = Viperfish; glc = Ghostlite; gfc = 6acc60406.

NOTE — append-and-insert, not append-only. New opcodes are inserted into the in-memory LloOpcode at their family's natural position (keeping families contiguous) but appended to the end of the LloOpcodeProto wire enum (preserving wire compatibility). This is why proto 498/499 map to low in-memory opcodes (0x084/0x197) — verified byte-exact. Port the actual LloOpcodeToProto table (0x344cb4c), not a formula. See LloOpcode↔Proto.

Verification Provenance

A representative sample of this table's value↔mnemonic↔slot bindings is grounded directly in the binary (classifiers, builders, converters). Probes (all CONFIRMED byte-exact):

Cross-References

• LLO Opcode Enum — the master family taxonomy, the opcode_info / opcode_info_big metadata tables, and the per-family value ranges this table consolidates.
• Sequencer Ops Per Gen — the per-(generation × sequencer-type) control-flow op inventory and the TpuSequencerType enum.
• InstBits Master DB — the LLVM-MC base-bits table (opcode − 499 index) that encodes only the BarnaCore subset.
• LloOpcode↔Proto — the wire-value converters and the 38 reserved proto gaps.
• ResultFifo / ArchRegister — the FIFO and physical-register enums the XLU/result-pop opcodes reference.
• MXU Slot · Matprep/IAR/Latch — matmul/latch/matprep/matres bit encoding and the IAR.
• VPU Slot · EUP / Transcendental Slot — vector-ALU and transcendental push/pop encoding.
• SPU / Scalar Slot · Sequencer Slot — scalar-ALU and PC-mutation encoding.
• Memory-Load · Memory-Store · CMEM-Load (PF) — the load/store/IAR slot encodings and the tier-by-slot model.
• Predicate Slot · vcreate_mask / M-Register — the scalar-predicate and vector-mask register files.
• Immediate Slot · Loop / LCC · Sparsity Slot (v5+) — immediate pool, loop counter, and the (open) sparsity slot.
• LLVM-TPU Intrinsic Table — the sibling appendix of llvm.tpu.* intrinsics that lower onto these opcodes.
• Per-Gen Comparison Matrix — the sibling appendix consolidating per-generation ISA deltas.