Glossary

All names and addresses on this page apply to libtpu.so from the libtpu-0.0.40-cp314 wheel (build-id 89edbbe81c5b328a958fe628a9f2207d; wheel/METADATA/__init__ version 0.0.40). The binary is not stripped: every C++ symbol survives as a demangled name, so a "term is grounded" claim here means the literal string or symbol is present in the binary's name/string tables. Other builds will differ.

Abstract

This is the canonical definition source for every acronym, codename, and term the rest of this wiki uses. It exists so that no other page has to re-define MXU, SCS, Mosaic, or gfc in passing — they link here, and here each term gets a tight one-to-three-sentence definition plus a pointer to the deep page that owns it. A reader who lands mid-graph on a page about, say, the SparseCore tile-execute sequencer can resolve TEC, Spmem, and vex here in seconds and then follow the link to the page that documents the mechanism.

The entries are grouped by domain — Silicon & Codenames, Compute Units, Memory Spaces, Compiler & IR, ABI & Runtime, Collectives & Network, Profiling, and Reverse-Engineering Terms — and within each group they read as a definition list. Every term that is a concrete binary fact (a codec namespace, a sequencer ordinal, a C-API struct) is anchored to the symbol, namespace, or ELF section that grounds it; terms that are external facts (the marketing name "Trillium", the conventional acronym "PSUM") or that are inferred carry an explicit (inferred) or (not in binary) tag rather than a fabricated anchor.

Two structural traps recur often enough to be worth stating before the body: a single TPU generation wears at least seven names spread across three numerically-disjoint integer axes (TpuVersion, DeviceType, TpuVersionProto), and the SparseCore sequencer enum exists in two off-by-one numberings (codec-template vs proto/runtime). Both are defined below and flagged where a reimplementer is most likely to index the wrong table.

For navigation, the contract is:

• Every binary-grounded term cites its grounding — a symbol, a namespace, an ELF section, or the owning deep page.
• Uncertain or external terms are flagged with (inferred), (external), or (not in binary); they are never given a fake address.
• The two recurring traps (the three-axis codename numbering and the two-numbering sequencer enum) get a callout where they live.

Silicon & Codenames

Three orthogonal naming systems describe one chip: the codec/ISA codename (a two-or-three-letter tag baked into namespaces), the fish codename (a marketing-adjacent internal name in .rodata), and the public Cloud name (v2…tpu7x). The codec codenames nest two levels deep under asic_sw::driver::deepsea:: — a family tag (jxc/pxc/vxc/gxc) then a fetch/load sub-core tag.

NOTE — the (N hits) figures throughout this page are name-table / sidecar substring hits — every occurrence of the token across the symbol-name index — not the deduped nm symbol counts. They are an order-of-magnitude relevance signal for "how much of the binary mentions this term," not a count of distinct functions or classes; a single class can contribute hundreds of hits through its members, vtables, and type-info strings. For a deduped population (e.g. the RTTI _ZTI/_ZTV/_ZTS census) use the Forensics Overview, which reports the nm-deduped totals. Do not add these hit counts together or read them as cardinalities.

GOTCHA — TpuVersion ≠ DeviceType. These are two enums maintained by two subsystems and were never meant to align. TpuVersion 4 is Ghostlite; DeviceType 4 is not any TPU generation. The DeviceType numbering is also chronologically inverted at the top: Ghostlite (older, v6e) = 13, 6acc60406 (newer, v7x) = 12. A reimplementer who indexes the profiler's per-device table with a compiler TpuVersion ordinal reads the wrong row. Resolve through Codename Cheat-Sheet.

NOTE — "Trillium", "Ironwood", "Ghostfish" are not in the binary. The literal strings have zero occurrences. The gxc::gfc abbreviation plausibly stands for a "Ghostfish"-style fish name, but that name is not present — cite 6acc60406 (internal) or TPU7x (display) instead. The Trillium = v6e = Ghostlite identity is correct but is an external (Cloud-documentation) fact.

Compute Units

The TensorCore is the dense-math engine; SparseCore is a separate co-processor for embedding/gather workloads, each with its own sequencer-typed ISA. Acronyms here name the per-slot functional units a bundle's slots target.

GOTCHA — 6acc60406 (gfc/v7x) ships SCS + TEC only, no TAC. Confirmed in the binary: gfc::isa::SparseCoreScs* (1,139 hits) and gfc::isa::SparseCoreTec* (17,193 hits) are present, but gfc::isa::SparseCoreTac* has zero hits. Viperfish (vfc) and Ghostlite (glc) carry all three sequencers; v7x drops the tile-access engine. A reimplementation that assumes a uniform SparseCore triad across all SparseCore-bearing generations emits a TAC codec the v7x hardware has no sequencer for. See GetSequencerType.

GOTCHA — the SparseCore sequencer enum has two off-by-one numberings. The codec template instantiates {SCS=3, TAC=4, TEC=5}; the proto/runtime form is one higher, {SCS=4, TAC=5, TEC=6}. TpuSequencerTypeFromProto is the literal internal = proto − 1 switch. Mixing the two silently encodes for the wrong engine (or for the reserved slot 2/3). See Sequencer Ops Per Gen.

Memory Spaces

A TPU program addresses several distinct, non-coherent memory spaces, each with its own allocator and addressing rules. The space is part of the LLO memory-space enum (see Memory-Space Enum); names below are the binary's own.

NOTE — PSUM is a convention, PartialSum is the binary. The wiki uses "PSUM" because it is the standard TPU term for the MXU accumulator banks, but the literal string PSUM does not appear; every binary anchor is to PartialSum. Do not search for PSUM and conclude the feature is absent.

Compiler & IR

The compiler ingests a high-level graph (HLO / StableHLO), lowers it through MLIR dialects (MHLO, the TPU dialect, Mosaic) to the per-bundle LLO target IR, schedules bundles, and assigns memory. Names below are the dialect/pass terms a compiler-pages reader meets.

ABI & Runtime

The plugin's external surface is the PJRT C-API, layered over the older TfTpu C-API. Runtime moves data in and out of the device via infeed/outfeed and executes async on streams.

Collectives & Network

Collective communication (all-reduce, all-gather, reduce-scatter) runs over ICI inside a pod and over the DCN across hosts. Topology terms below describe the fabric a collective is scheduled onto.

Profiling

The profiler emits the Google XProf schema — a proto-defined event tree (XSpace → XPlane → XEvent + XStat) — with per-core trace dispatchers, one per sub-core type. Terms below name that schema.

Reverse-Engineering Terms

These are the static-analysis terms the wiki uses to describe how a fact was recovered from the binary, not facts about the TPU itself.

Cross-References

• Codename Cheat-Sheet — the canonical card binding every codename across all three integer axes; come here first for any jxc/glc/DeviceType question
• Subsystem Map — the top-level layout these terms are grouped by
• ISA Overview · Memory-Space Enum · Bundle Model Overview — owns the compute-unit, memory-space, and bundle terms
• Memory Overview — owns HBM/VMEM/SMEM/CMEM/SFLAG/MRB
• SparseCore Overview · GetSequencerType — owns SCS/TAC/TEC and the two-numbering trap
• Compiler Overview · Mosaic Overview · MSA Overview — owns HLO/MHLO/StableHLO/Mosaic/LLO/MSA
• PJRT Overview · API Vtable Reconstruction — owns the PJRT/TfTpu ABI terms
• Collectives Overview · ICI Overview · Megascale Overview — owns ICI/DCN/Megascale/superpod
• Profiling Overview · XPlane / XStat / TraceMe — owns the XProf schema terms
• Forensics Overview · RTTI/Vtable Census · ELF Anatomy — owns the reverse-engineering vocabulary