cl::opt Full Catalog

Every command-line option the tileiras binary registers — through LLVM cl::opt / cl::list / cl::alias, the NVIDIA-private dialect-bag, and MLIR PassOption registrars that share its textual surface. An option counts if a static-storage symbol calls llvm::cl::Option::setArgStr(name, len) (sub_4534CC0, 1174 B) at static-construction time, if a tileiras dialect-bag helper (sub_5FE350 / sub_5FE910 / sub_5FED40) runs from a per-invocation builder, or if mlir::detail::PassOptions::Option<T> is constructed from sub_6D3460. The binary contains 689 distinct caller addresses for sub_4534CC0; this catalog covers the 77 user-visible options across registrars 1–7. The 478-row PassBuilder name registry is summarized in PassBuilder Mega-Registry.

Reading guide

Option families surface to the user through different CLI prefixes. The first stop depends on which prefix appears on the command line:

When the same name appears in two layers (the documented --compute-capability collision between Layer 2 and Layer 3 is the canonical example), the driver propagates the Layer-2 value down into Layer 3; the Layer-3 default fires only when the MLIR pass library is loaded outside the tileiras driver.

Registrar Tiers

The static-init-time CLI surface partitions into five disjoint registrars plus two LLVM-inherited bulk registrars. Each tier owns its builder body, its storage scheme, and its help-text rodata cluster.

Static-init order follows ELF .init_array; each ctor invokes setArgStr(opt, name, len) then done() (sub_4534420, 199 B), inserting into cl::GlobalParser (sub_4530050). Categories attach via sub_452D690 (OptionCategory::addOption, 455 B). The atomic counter NumOccurrences (sub_452D580, 88 B) uses InterlockedExchangeAdd64. Standard cl::alias diagnostics live at 0x45E7218/0x45E7258/0x45E7288/0x45E72C0 (verbatim upstream) and route through sub_452D9F0 → sub_459CCA0; the duplicate-registration error " registered more than once!" is emitted from setArgStr itself.

Master Table

Columns: option | type | default | help text (verbatim) | storage / agg offset | defining pass / TU | wiki page. Sorted alphabetically within each registrar. Where the per-option BSS storage was not individually extracted, the rodata address of the name string is given as name@<addr>.

Layer 1 — Tileiras Driver Globals (registrar sub_579270)

Aggregate: heap-allocated 864 B TileirasDriverCLOpts, owner pointer returned to main via sub_57A170. cl::opt slots are 192 B; the two cl::alias slots are 136 B. Applicator trampolines are sub_578C40 (int) and sub_578C50 (bool), paired with nullsub_10 / nullsub_11.

--opt-level ValueStr metavar = "N" (renders as --opt-level=<N>). Aggregate heap-allocated by sub_44A8C20(0x360).

Layer 1 — cl::ValuesClass int32 enum options

Four additional Layer-1 options are wired by byte-equivalent template instantiations of cl::opt<cl::ValuesClass>::opt, each differing only in its string-pair table, parser vtable, and the int32 target slot it writes into the aggregate. The parsed result is always a single int32; downstream code consults the integer, never the string.

GPU-name codes correspond to compute-capability families: 100 is Datacenter Blackwell (default), 103 the Blackwell variant, 110 Jetson Thor, 120 Consumer RTX 50** / Pro, 121 DGX Spark. --sanitize is the toggle that activates the -sanitize=memcheck -g-tmem-access-check nvdisasm tail.

Host-triple resolution reads these ints downstream. sub_40FD330 keys off the host-arch int with stride 39 for x86_64 (code 0), stride 36 for aarch64 (code 1), and stride 36 for arm64ec (code 2 — which uses a sub-entry of the aarch64 record); this is the only place arm64ec diverges from aarch64. sub_40FD7E0 keys off the host-os int with OS-index 7 for linux (code 0) and OS-index 15 for windows (code 1).

The four parser vtables &unk_59A7378 / &unk_59A7468 / &unk_59A7558 / &unk_59A7648 share an 8-slot layout: vtable+0 typeinfo helper, +8 destructor, +16 parse (string → int32 map probe), +24 print (int32 → string lookup), +32 valuesDefault (initialise from a cl::values(...) builder), +40 reserved, +48 reserved, +56 reserved. The parse slot is the only operation invoked at command-line-parse time; the print slot fires only when --help is requested.

Layer 2 — Tileiras Dialect Options Bag (registrar sub_602440)

Aggregate: ~1488 B heap-allocated dialect bag attached to a per-invocation mlir::DialectRegistry. Not visible through the global LLVM parser; consumed by tileiras's pre-driver loop and forwarded to Layer 3. Helpers: sub_5FE350 (enum), sub_5FE910 (string), sub_5FED40 (bool).

Enum table for --debuginfo-level (constructed inline by sub_602440):

Note: --compute-capability collides with the Layer-3 PassOption of the same name (Layer 2 defaults to sm_100, Layer 3 to sm_80). The driver propagates Layer 2 into Layer 3; the Layer-3 default fires only when the MLIR passes load without the tileiras driver.

Layer 3 — TileIR MLIR PassOptions (registrar sub_6D3460)

20 mlir::Pass::Option<T> registrations on a single TileIRPipelineOptions (≥5616 B). Not in the global LLVM cl::opt registry; parsed from --pass-pipeline="tileir{key=value ...}". reg+N is the registration slot (208 B stride); val+N is the resolved-value offset in the a2 value-struct read by sub_6D6A00. For per-option consumer mapping see Options Mapping.

Enum tables for Layer-3 enums:

Layer 4 — NVPTX Backend cl::opt (LLVM static ctors)

Per-TU global ctors invoking sub_4534CC0(&optObj, name, len) at static-init. Eight rows below are INITIALIZE_PASS markers (pass-name registrations, not cl::opt). The set is verbatim upstream LLVM NVPTXTargetMachine; default for nvptx-force-min-byval-param-align is patched to false (upstream = true).

Layer 4 also carries nvptx-prec-divf32 enum value-strings: Use div.approx, Use div.full, Use IEEE Compliant F32 div.rnd if available (default), Use IEEE Compliant F32 div.rnd if available, no FTZ.

Layer 4b — NVPTX-CL Options Registrar (sub_45BA4C0)

A ManagedStatic-guarded static initializer at sub_45BA4C0 (8524 B) registers exactly 13 llvm::cl::opt instances against the global registry. Each branch ends with __cxa_atexit(dtor, &opt, &__dso_handle). These appear bare on the CLI (no -mllvm prefix).

Layer 5 — NVVM Reflect cl::opt (ctor_238 at 0x463A70)

Three registrations bundled into one TU ctor: a cl::opt<bool>, a cl::list<std::string>, and a cl::alias. List backing std::vector<std::string> at 0x5B4F380 (begin/end) + 0x5B4F390 (capacity); 32 B/entry. Atexit dtors: sub_9C31D0 (opt), sub_9C3B10 (list), sub_9C3120 (alias).

Two pass-name strings co-locate in Layer 5 but register via INITIALIZE_PASS, not cl::opt:

The legacy-PM create-fn for nvvm-reflect (sub_1BD0880, 21 B) is a report_fatal_error("target-specific codegen-only pass") stub; the real pass body reaches through the new-PM path in sub_1A92780. Three soft-CLI parser errors live at 0x4D3C6B8 / 0x4D3C6E0 / 0x4D3C710 (Empty name, Missing value, integer value expected in nvvm-reflect-add option ').

The 13 B string nvvm-reflect- at 0x4D3C6A0 has ftz\0 at offset +13 (0x4D3C6AD), so a 16 B StringRef into Module::getModuleFlag materializes the key "nvvm-reflect-ftz" from concatenated rodata. The same ftz substring is shared with the Layer-3 ftz PassOption.

Layer 6 — MLIR Framework cl::opt (AsmPrinter / Diagnostics / PassManager / Timing)

18 static-ctor cl::opts in MLIR support libs (lib/IR/AsmPrinter.cpp, lib/IR/Diagnostics.cpp, lib/IR/MLIRContext.cpp, lib/Pass/PassTiming.cpp). Exposed unmodified through the global LLVM cl::opt parser.

Enum values — mlir-timing-display: list = display the results in a list sorted by total time (0x502F5F0); tree = display the results ina with a nested tree view (0x502F628, verbatim typo ina preserved from upstream). mlir-output-format: text = display the results in text format (0x502F658); json = display the results in JSON format (0x502F680).

Layer 7 — Misc LLVM cl::opt

PassBuilder Mega-Registry Note

• The 478 pretty-name-keyed ("llvm::TPass]") entries + 66 naked-class entries + 7 special-form entries (551 total) inserted into the PassBuilder StringMap<PassInfo> by sub_1CCB7D0 (35948 B) are downstream LLVM. Twenty NVIDIA-private interleavings (check-gep-index, check-kernel-functions, cnp-launch-check, ipmsp, nv-early-inliner, nv-inline-must, nvvm-pretreat, nvvm-verify, printf-lowering, select-kernels, nvvm-aa, kernel-info, nvvm-reflect-pp, nvvm-peephole-optimizer, propagate-alignment, reuse-local-memory, memory-space-opt, lower-aggr-copies, lower-struct-args, process-restrict) are pipeline-text-parser keys for --passes=..., not freestanding cl::opts; factory functors live in parseModulePass / parseCGSCCPass / parseFunctionPass / parseLoopPass / parseMachinePass. Full table: pipeline/passbuilder-mega-registry.