Extended Glossary

All names and symbols on this page apply to libtpu.so from the libtpu-0.0.40-cp314 wheel (build-id 89edbbe81c5b328a958fe628a9f2207d). The binary is not stripped: every C++ symbol survives as a demangled name, so a "term is grounded" claim here means the literal string or symbol is present in the binary's name/string tables. The parenthetical hit counts are nm name-table line counts (symbols whose demangled name contains the term) against this exact build; other builds will differ.

Abstract

This is the long-tail companion to the root Glossary. The root page is the tight ~83-term quick reference — codenames, compute units, memory spaces, IR names, ABI terms — the vocabulary every page links back to. This page is the deep-reference index of named things: the concrete struct/class names, the enum families, the ISA-page abbreviations, the profiler/trace nouns, and the collective/network terms that a reimplementer meets only once they are inside the deep ISA, cost-model, scheduler, routing, and profiling pages. None of these warranted a slot in the quick reference, but every one of them is a symbol a reader will eventually grep for and need defined.

The split is deliberate and non-overlapping. The root glossary defines MXU, SCS, LLO, PJRT, HBM, TpuVersion. This page defines the implementation surface below those: the tpu::Target capability object the codename axis resolves to, the CycleTable/MxuLatencyTable pair the cost model reads, the MatmulModeAttr/GainLatchModeAttr MLIR enums the MXU slot encodes, the Iar/Msr/Lmr register abbreviations the matrix-push pipeline cycles through, the XLineBuilder/GtcSpan trace plumbing, and the TwistedTorusND/ToroidalRouteCache/VirtualChannel routing machinery. If the root glossary answers "what does this acronym mean," this page answers "what is the named C++ entity behind it, and which page owns it."

Every entry that names a concrete binary entity was re-confirmed against the name table before being defined; the parenthetical hit counts are nm name-table line counts (symbols whose demangled name contains the term). A handful of terms that recur in TPU collective literature but are not present as TPU symbols in this binary (most notably RDH) are kept as flagged absences so a later page does not silently treat them as grounded. Definitions stay to one or two sentences plus a deep-page pointer; the deep page owns the algorithm, the layout, and the rationale.

For navigation, the contract is:

• This page EXTENDS, never duplicates, the root Glossary — the 83 quick-reference terms live there; do not re-define MXU/SCS/LLO/PJRT/HBM here.
• Every binary-grounded term cites its grounding — a class symbol, an enum, an Attr storage, or the owning deep page.
• Uncertain or external terms are flagged with (inferred), (external), or (not in binary); they are never given a fake anchor.
• Each term ends in a pointer to the deep page that owns its mechanism.

Structs & Classes

The named C++ types a reimplementer instantiates or models. These are the spine of the deep pages — the capability object the codename resolves to, the cost tables, the IR builders, and the allocators. Grounding is the demangled class symbol.

NOTE — tpu::Target is the real "codename" payload. The root glossary's three integer axes (TpuVersion / DeviceType / TpuVersionProto) are just selectors; the object they select is a tpu::Target (or SparseCoreTarget). A reimplementer who treats the codename as an enum and stops there misses that every per-generation constant — accumulator count, sublane mask, scoped-memory limit, bank-conflict rule — lives as a Target accessor, not in a flat table.

Enum Families

The enum families the ISA pages encode. In this binary the per-bundle ISA enums are realized as MLIR enum attributes — each is a …Attr with a …AttrStorage (e.g. MatmulModeAttr, MatmulModeAttrStorage), so a grep for the bare name plus Attr confirms it is an op-attribute enum rather than a plain C enum. Grounding is the attribute symbol.

GOTCHA — these are op-attributes, not flat C enums. Each Matmul*/GainLatchMode/Vxpose enum exists as an MLIR …Attr with a generated …AttrStorage and a …AndScalingFactor companion. A reimplementer encoding the bundle from a plain integer enum will miss the paired scaling-factor/storage that the attribute carries — the data format and the gain mode are latched together (MatmulDataFormatAndScalingFactor, GainLatchModeAndScalingFactor), not independently.

ISA Abbreviations

The short register/latch abbreviations that the ISA-slot pages use without expansion. Each is the matrix-push / encoder pipeline's name for a specific hardware register class or latch state. Grounding is the camel-cased symbol family — note the binary uses CamelCase (Iar, Msr), so an uppercase grep (IAR) returns zero.

NOTE — casing matters when grepping the name table. A literal IAR (all-caps) has zero hits; the grounded symbol is the CamelCase Iar (4,793 hits). Likewise MatPush is absent — the binary spells it Matpush (97). Grep with the binary's casing, or you will conclude a feature is missing when it is not.

Profiling Terms

The named nouns in the trace/profiling plumbing below the root glossary's XProf-schema entries (XPlane/XEvent/XStat/XSpace/TraceMe). These are the builders and spans a profiler-page reader meets. Grounding is the class symbol.

Collective Terms

The fabric/topology nouns a collectives or routing page uses. Several are realized as the routing classes already listed under Structs (TwistedTorusND, ToroidalRouteCache); the entries here are the descriptive terms and the VirtualChannel machinery. Grounding is noted per row.

NOTE — twisted torus, n-hop, and megacore are the resiliency triad here. When an ICI link or a sub-cube fails, the routing layer reaches a working path by combining the twisted-torus shear, n-hop multi-link routing, and (for compute) the megacore even/odd split — all three grounded above. The conventional "RDH" framing is not how this binary names that mechanism.

Misc

Terms that span clusters or name reverse-engineering artifacts a deep-page reader meets.

Cross-References

• Glossary — the parent quick reference; the ~83 core terms (codenames, compute units, memory spaces, IR names, ABI terms) live there, and this page extends them. Resolve MXU/SCS/LLO/PJRT/HBM there, the named structs/enums/abbreviations here.
• Codename Cheat-Sheet — the canonical three-axis codename card; what tpu::Target is ultimately selected by.
• ISA Overview · MXU Slot · Memory-Space Enum · ResultFifo / ArchRegister · MatPrep / IAR Latch Slot — owns the enum families and the IAR/MRB/MSR/LMR/CBREG/RPU abbreviations.
• Cost Overview · CycleTable Family · MXU Latency Overview · Matmul Mode Modifiers — owns CycleTable, MxuLatencyTable, and the matmul-mode cost modifiers.
• Scheduler Overview · MRB Chain Allocator · MRB FIFO / MSR Placement · Encoder Latch Serialization — owns MrbChainAllocator, MRB/MSR placement, and the LSF latch.
• Profiling Overview · Trace Entries Coder · Riegeli Trace Container · XPlane / XStat / TraceMe — owns TraceEntry, XLine/XLineBuilder, GtcSpan, and riegeli.
• Collectives Overview · Twist Overview · Routing Overview · VC Balance Allocation — owns TwistedTorusND, ToroidalRouteCache, VirtualChannel, megacore, and n-hop routing.
• Targets Overview · Target Capability Bitfield · SparseCore Target Descriptor · TpuTopology Struct — owns tpu::Target, SparseCoreTarget, TpuCoreParts, and TpuTopology.